KR970054016A - Method for forming charge storage electrode of semiconductor device - Google Patents
Method for forming charge storage electrode of semiconductor device Download PDFInfo
- Publication number
- KR970054016A KR970054016A KR1019950050983A KR19950050983A KR970054016A KR 970054016 A KR970054016 A KR 970054016A KR 1019950050983 A KR1019950050983 A KR 1019950050983A KR 19950050983 A KR19950050983 A KR 19950050983A KR 970054016 A KR970054016 A KR 970054016A
- Authority
- KR
- South Korea
- Prior art keywords
- charge storage
- storage electrode
- forming
- conductive film
- oxide layers
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims abstract description 6
- 239000004065 semiconductor Substances 0.000 title claims abstract 4
- 238000001039 wet etching Methods 0.000 claims abstract 4
- 238000000151 deposition Methods 0.000 claims abstract 2
- 238000001312 dry etching Methods 0.000 claims abstract 2
- 238000005530 etching Methods 0.000 claims abstract 2
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
- H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
- H01L28/91—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions made by depositing layers, e.g. by depositing alternating conductive and insulating layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/75—Electrodes comprising two or more layers, e.g. comprising a barrier layer and a metal layer
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Memories (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
본 발명은 반도체 소자의 전하저장전극 형성 방법에 있어서; 전하저장전극 콘택홀을 형성하고 전하저장전극용 제1전도막을 형성하는 단계; 상기 제1전도막 상에 소정 용액에서 습식식각 선택비가 서로 다른 다수의 산화막을 적층 형성하는 단계; 전하저장전극 마스크를 형성하고 상기 산화막들 및 제1전도막을 건식식각 하는 단계; 상기 전하저장전극 마스크가 형성된 상태에서 상기 산화막들을 습식식각하여 산화막들의 측벽이 요철 형상을 갖도록 하는 단계; 상기 전하저장전극 마스크를 제거하는 단계; 전체구조 상부에 전하저장전극용 제2전도막을 증착하고 다시 전면 식각하여 상기 요철진 산화막들의 측벽에 제2전도막 기둥을 형성하는 단계; 및 상기 산화막들을 제거하는 단계를 포함하는 것을 특징으로 하는 반도체 소자의 전하저장전극 형성 방법에 관한 것으로, 실린더 형태의 모양을 갖되 단차가 크게 발생하지 않으면서 표면적이 증대되어, 고집적 메모리 소자의 캐패시턴스 확보 및 후속 공정을 용이하게 할 수 있다.The present invention provides a method for forming a charge storage electrode of a semiconductor device; Forming a charge storage electrode contact hole and forming a first conductive film for the charge storage electrode; Stacking a plurality of oxide films having different wet etching selectivity in a predetermined solution on the first conductive film; Forming a charge storage electrode mask and dry etching the oxide layers and the first conductive layer; Wet etching the oxide layers while the charge storage electrode mask is formed so that sidewalls of the oxide layers have irregularities; Removing the charge storage electrode mask; Depositing a second conductive film for the charge storage electrode on the entire structure and etching the entire surface to form a second conductive film pillar on sidewalls of the uneven oxide films; And removing the oxide layers, wherein the charge storage electrode forming method of the semiconductor device comprises a cylindrical shape, the surface area of which is increased without a large step, thereby ensuring capacitance of the highly integrated memory device. And subsequent processes can be facilitated.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.
제3a도 및 제3b도는 본 발명의 일실시예에 따른 전하저장전극 형성 공정도.3a and 3b is a process chart of forming a charge storage electrode according to an embodiment of the present invention.
Claims (1)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950050983A KR0172771B1 (en) | 1995-12-16 | 1995-12-16 | Storage electrode fabrication method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950050983A KR0172771B1 (en) | 1995-12-16 | 1995-12-16 | Storage electrode fabrication method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR970054016A true KR970054016A (en) | 1997-07-31 |
| KR0172771B1 KR0172771B1 (en) | 1999-02-01 |
Family
ID=19440768
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019950050983A KR0172771B1 (en) | 1995-12-16 | 1995-12-16 | Storage electrode fabrication method |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR0172771B1 (en) |
-
1995
- 1995-12-16 KR KR1019950050983A patent/KR0172771B1/en not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| KR0172771B1 (en) | 1999-02-01 |
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| Date | Code | Title | Description |
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| A201 | Request for examination | ||
| E701 | Decision to grant or registration of patent right | ||
| GRNT | Written decision to grant | ||
| FPAY | Annual fee payment |
Payment date: 20050922 Year of fee payment: 8 |
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| LAPS | Lapse due to unpaid annual fee |