KR970053919A - Manufacturing Method of CMOS Field Effect Transistor - Google Patents

Manufacturing Method of CMOS Field Effect Transistor Download PDF

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KR970053919A
KR970053919A KR1019950066087A KR19950066087A KR970053919A KR 970053919 A KR970053919 A KR 970053919A KR 1019950066087 A KR1019950066087 A KR 1019950066087A KR 19950066087 A KR19950066087 A KR 19950066087A KR 970053919 A KR970053919 A KR 970053919A
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South Korea
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effect transistor
field effect
manufacturing
impurity region
transistor according
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KR1019950066087A
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Korean (ko)
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KR0180785B1 (en
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김미란
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김주용
현대전자산업주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823892—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

본 발명은 씨모스 전계효과 트랜지스터의 제조방법에 관한 것으로서, 고에너지 이온주입 공정시 다중 이온주입후 웰 이온확산 열처리를 두 번째 희생산화 공정과 동시에 진행하였으므로, 공정을 단순화 하고 소자의 리플레쉬 특성을 개선하여 공정수율 및 소자 동작의 신뢰성을 향상시킬 수 있다.The present invention relates to a method for manufacturing a CMOS field effect transistor, and in the high energy ion implantation process, the well ion diffusion heat treatment is performed simultaneously with the second sacrificial oxidation process after the multi-ion implantation, thereby simplifying the process and improving the refresh characteristics of the device. By improving the process yield and the reliability of device operation can be improved.

Description

씨모스 전계효과 트랜지스터의 제조방법Manufacturing Method of CMOS Field Effect Transistor

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제2a도 내지 제2e도는 본 발명에 따른 CMOS FET의 제조 공정도.2a to 2e are manufacturing process diagrams of the CMOS FET according to the present invention.

Claims (16)

반도체기판의 일정상부에 소자분리산화막을 형성하는 공정과, 상기 구조의 전표면에 제1희생산화막을 형성하는 공정과, 상기 반도체기판에서 N웰로 예정되어있는 부분에 N-웰 불순물영역과 P-채널 필드 스톱 불순물영역 및 P-채널 깊은 불순물영역을 형성하는 공정과, 상기 반도체가판에서 P-웰로 예정되어있는 부분에 P-웰 불순물영역 및 N-채널 깊은 불순물영역을 형성하는 공정과, 상기 제1희생산화막을 제거하는 공정과, 상기 불순물영역의 불순물들을 활성화 시키는 열처리와 동시에 제2희생산화막을 형성하는 공정과, 상기 N-웰에 블란켓 Vt로 N채널 Vt 불순물 영역을 형성하는 공정과, 상기 P-웰에 P-채널 Vt불순물영역을 형성하는 공정과, 상기 제2희생산화막을 제거하는 공정과, 상기 N-웰 과 P-웰 쪽에 각각 게이트 산화막과 게이트전극 및 소오스/드레인 영역을 형성하는 공정을 구비하는 씨모스 전계효과 트랜지스터의 제조방법.Forming a device isolation oxide film on a predetermined portion of the semiconductor substrate, forming a first rare production film on the entire surface of the structure, and N-well impurity region and P- Forming a channel field stop impurity region and a P-channel deep impurity region, forming a P-well impurity region and an N-channel deep impurity region in a portion of the semiconductor substrate designated as a P-well; Removing the one rare production film, forming a second rare production film simultaneously with heat treatment activating impurities in the impurity region, forming an N-channel Vt impurity region with a blanket Vt in the N-well; Forming a P-channel Vt impurity region in the P-well, removing the second rare oxidized film, and a gate oxide film, a gate electrode, and a source / drain on the N-well and P-well, respectively. A method for manufacturing a CMOS field effect transistor, comprising the step of forming a phosphorus region. 제1항에 있어서, 상기 소자분리 산화막을 900∼1200℃에서 3000∼4000Å 두께로 형성하는 것을 특징으로하는 씨모스 전계효과 트랜지스터의 제조방법.The method of manufacturing a CMOS field effect transistor according to claim 1, wherein the device isolation oxide film is formed at a thickness of 3000 to 4000 kPa at 900 to 1200 占 폚. 제1항에 있어서, 상기 제1희생산화막을 100∼200Å 두께로 형성하는 것을 특징으로하는 씨모스 전계효과 트랜지스터의 제조방법.The method of manufacturing a CMOS field effect transistor according to claim 1, wherein the first rare production film is formed to a thickness of 100 to 200 kHz. 제1항에 있어서, 상기 N-웰 불순물영역을 500KeV∼2.5MeV의 이온주입에너지로, 1.0E13∼4.0E13/㎠의 도우즈 양으로 이온주입하는 것을 특징으로하는 씨모스 전계효과 트랜지스터의 제조방법.The method of manufacturing a CMOS field effect transistor according to claim 1, wherein the N-well impurity region is ion implanted with an ion implantation energy of 500 KeV to 2.5 MeV at a dose amount of 1.0E13 to 4.0E13 / cm 2. . 제1항에 있어서, 상기 P-채널 필드스톱 불순물영역을 100∼500keV 에너지로, 1.0E12∼1.0E13/㎠의 도우즈 양으로 형성하는 것을 특징으로 하는 씨모스 전계효과 트랜지스터의 제조방법.The method of manufacturing a CMOS field effect transistor according to claim 1, wherein the P-channel field stop impurity region is formed with a dose amount of 1.0E12 to 1.0E13 / cm 2 with energy of 100 to 500 keV. 제1항에 있어서, 상기 P-채널 깊은 불순물영역을 10∼100keV 에너지로 5.0E11∼5.0E12/㎠의 도우즈양으로 형성하는 것을 특징으로하는 씨모스 전계효과 트랜지스터의 제조방법.The method of manufacturing a CMOS field effect transistor according to claim 1, wherein the P-channel deep impurity region is formed in a dose amount of 5.0E11 to 5.0E12 / cm 2 at 10 to 100 keV energy. 제1항에 있어서, 상기 P-웰을 400keV∼1MeV 에너지로 1.0E13∼5.0E13/㎠의 도우즈 양으로 형성하는 것을 특징으로하는 씨모스 전계효과 트랜지스터의 제조방법.The method of manufacturing a CMOS field effect transistor according to claim 1, wherein the P-well is formed in a dose amount of 1.0E13 to 5.0E13 / cm 2 at 400 keV to 1MeV energy. 제1항에 있어서, N-채널 깊은 불순물영역을 60∼400keV 에너지로 5.0E11∼1.0E13/㎠의 도우즈양으로 형성하는 것을 특징으로하는 씨모스 전계효과 트랜지스터의 제조방법.The method of manufacturing a CMOS field effect transistor according to claim 1, wherein the N-channel deep impurity region is formed in a dose amount of 5.0E11 to 1.0E13 / cm 2 at 60 to 400 keV energy. 제1항에 있어서, 상기 불순물 활성화를 위한 열처리 공정을 800∼1100℃에서 30분∼2시간에 걸쳐 실시하는 것을 특징으로하는 씨모스 전계효과 트랜지스터의 제조방법.The method of manufacturing a CMOS field effect transistor according to claim 1, wherein the heat treatment step for activating the impurity is performed at 800 to 1100 ° C. for 30 minutes to 2 hours. 제1항에 있어서, 상기 제2희생산화막을 50∼300Å 두께로 형성하는 것을 특징으로하는 씨모스 전계효과 트랜지스터의 제조방법.2. The method of manufacturing a CMOS field effect transistor according to claim 1, wherein the second rare production film is formed to a thickness of 50 to 300 kHz. 제1항에 있어서, 상기 제2희생산화막을 750∼950℃ 온도에서 형성하는 것을 특징으로하는 씨모스 전계효과 트랜지스터의 제조방법.2. The method for manufacturing a CMOS field effect transistor according to claim 1, wherein the second rare production film is formed at a temperature of 750 to 950 占 폚. 제1항에 있어서, 상기 희생산화막 형성 후, 블란켓 Vt 불순물영역을 형성하는 것을 특징으로하는 씨모스 전계효과 트랜지스터의 제조방법.The method for manufacturing a CMOS field effect transistor according to claim 1, wherein after forming said sacrificial oxide film, a blanket Vt impurity region is formed. 제12항에 있어서, 상기 블란켓 Vt 불순물영역을 10keV∼60keV 에너지로 3.0E11∼5.0E12/㎠의 도우즈양으로 형성하는 것을 특징으로하는 씨모스 전계효과 트랜지스터의 제조방법.13. The method of manufacturing a CMOS field effect transistor according to claim 12, wherein the blanket Vt impurity region is formed in a dose amount of 3.0E11 to 5.0E12 / cm2 at 10keV to 60keV energy. 제1항에 있어서, 상기 P-채널 Vt 이온주입과 셀 Vt 이온주입을 동시에 행하는 것을 특징으로 하는 씨모스 전계효과 트랜지스터의 제조방법.The method of manufacturing a CMOS field effect transistor according to claim 1, wherein the P-channel Vt ion implantation and the cell Vt ion implantation are performed simultaneously. 제1항에 있어서, 상기 P-채널 Vt 이온주입과 셀 Vt 이온주입시 10keV∼60keV 에너지이고,5.0E11∼5.0E12/㎠의 도우즈 양으로 형성하는 것을 특징으로하는 씨모스 전계효과 트랜지스터의 제조방법.The CMOS field effect transistor according to claim 1, wherein the P-channel Vt ion implantation and the cell Vt ion implantation have energy of 10 keV to 60 keV and are formed in a dose amount of 5.0E11 to 5.0E12 / cm 2. Way. 제1항에 있어서, 상기 N-웰, P-채널 필드스톱, P-채널 깊은 불순물영역, P-웰 이온주입, N-채널 기픈 이온주입의 주입각을 0∼9°로 하는 것을 특징으로하는 씨모스 전계효과 트랜지스터의 제조방법.The implant angle of the N-well, the P-channel field stop, the P-channel deep impurity region, the P-well ion implantation, and the N-channel open ion implantation is 0 to 9 °. Method of manufacturing CMOS field effect transistor. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950066087A 1995-12-29 1995-12-29 Method for manufacturing cmos field transistor KR0180785B1 (en)

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