KR970053886A - CMOS device manufacturing method - Google Patents

CMOS device manufacturing method Download PDF

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Publication number
KR970053886A
KR970053886A KR1019950046374A KR19950046374A KR970053886A KR 970053886 A KR970053886 A KR 970053886A KR 1019950046374 A KR1019950046374 A KR 1019950046374A KR 19950046374 A KR19950046374 A KR 19950046374A KR 970053886 A KR970053886 A KR 970053886A
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South Korea
Prior art keywords
conductive
forming
diffusion
impurity ions
gate
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KR1019950046374A
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Korean (ko)
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KR100192518B1 (en
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손정환
이상돈
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문정환
Lg 반도체 주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H01L21/823842—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors

Abstract

본 발명은 CMOS 소자 제조방법에 관한 것으로, 듀얼(Dual) 게이트 CMOS 소자에 있어서, 게이트 폴리에 이온주입된 보론(Boron)이 채널영역으로 확산되는 것을 방지하는데 적당한 CMOS 소자 제조방법을 제공하기 위한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for fabricating a CMOS device, and to provide a method for fabricating a CMOS device suitable for preventing diffusion of boron ion implanted into a gate poly into a channel region in a dual gate CMOS device. .

이를 위한 본 발명의 CMOS 소자 제조방법은 제1도전형 반도체 기판에 제2도전형 웰을 형성하여, 제1, 제2도전형 모오스 영역을 정의한 후 게이트 산화막과 필드 산화막을 형성하는 단계, 전면에 다결정 실리콘층을 형성한 후, 제2도전형 불순물 이온이 채널쪽으로 확산되는 것을 방지하기 위해 상기 다결정 실리콘층에 확산방지용 불순물 이온주입을 실시하는 단계, 상기 제1, 제2도전형 모오스 영역에 해당 도전형 저농도 불순물 이온주입을 실시한 후 각각의 게이트 측벽을 형성하는 단계, 상기 제1, 제2도전형 모오스 영역에 해당 도전형 고농도 불순물 이온주입을 실시하여 각각 LCD 구조를 갖는 MOS FET를 형성하는 단계를 포함하여 이루어짐을 특징으로 한다.In the CMOS device fabrication method of the present invention, the second conductive well is formed on the first conductive semiconductor substrate, the first and second conductive mos regions are defined, and then the gate oxide and the field oxide are formed. After forming the polycrystalline silicon layer, performing diffusion preventing impurity ion implantation into the polycrystalline silicon layer to prevent the diffusion of the second conductive impurity ions toward the channel, and corresponds to the first and second conductive moieties Forming each gate sidewall after conducting the conductive low concentration impurity ion implantation, and performing the conductive high concentration impurity ion implantation in the first and second conductive moiety regions to form MOS FETs having LCD structures, respectively. Characterized in that comprises a.

Description

씨모오스(CMOS) 소자 제조 방법CMOS device manufacturing method

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도 (a)∼(b)는 본 발명의 제1실시예에 따른 CMOS 소자 제조방법을 나타낸 공정단면도.2 (a) to 2 (b) are process cross-sectional views showing a method of manufacturing a CMOS device according to the first embodiment of the present invention.

Claims (6)

제1도전형 반도체 기판에 제2도전형 웰을 형성하여, 제1, 제2도전형 모오스 영역을 정의한 후 게이트 산화막과 필드 산화막을 형성하는 단계, 전면에 다결정 실리콘층을 형성한 후, 제2도전형 불순물 이온이 채널쪽으로 확산되는 것을 방지하기 위해 상기 다결정 실리콘층에 확산방지용 불순물 이온주입을 실시하는 단계, 상기 제1, 제2도전형 모오스 영역에 해당 도전형 저농도 불순물 이온주입을 실시한 후 각각의 게이트 측벽을 형성하는 단계, 상기 제1, 제2도전형 모오스 영역에 해당 도전형 고농도 불순물 이온주입을 실시하여 각각 LDD 구조를 갖는 MOS FET를 형성하는 단계를 포함하여 이루어짐을 특징으로 하는 CMOS 소자 제조 방법.Forming a second conductive well on the first conductive semiconductor substrate to define the first and second conductive MOSFET regions, forming a gate oxide film and a field oxide film, forming a polycrystalline silicon layer on the entire surface, and then Performing diffusion preventing impurity ion implantation into the polycrystalline silicon layer to prevent diffusion of the conductive impurity ions into the channel, and then performing a conductive low concentration impurity ion implantation into the first and second conductive mos Forming a gate sidewall of the semiconductor device, and forming a MOS FET having an LDD structure by implanting the conductive high concentration impurity ions into the first and second conductive MOS regions, respectively. Manufacturing method. 제1항에 있어서, 상기 확산방지용 불순물은 게르마늄(Germanium)과 니트로겐(Nitrogen)을 포함함을 특징으로 하는 CMOS 소자 제조 방법.The method of claim 1, wherein the diffusion preventing impurity comprises germanium and nitrogen. 제2항에 있어서, 상기 게르마늄과 니트로겐은 동시에 이온주입함을 특징으로 하는 CMOS 소자 제조 방법.The method of claim 2, wherein the germanium and the nitrogen are ion implanted at the same time. 제1도전형 반도체 기판에 제2도전형 웰을 형성하여, 제1, 제2도전형 모오스 영역을 정의한 후 게이트 산화막과 필드 산화막을 형성하는 단계, 전면에 다결정 실리콘층을 형성한 후 하기의 제2도전형 불순물 이온이 채널영역으로 확산되는 것을 방지하기 위해 상기 다결정 실리콘층에 확산방지용 제1순물 이온주입을 실시하는 단계, 상기 제1, 제2도전형 모오스 영역에 해당 도전형 저농도 불순물 이온주입을 실시한 후 각각의 게이트 측벽을 형성하는 단계, 상기 제1, 제2도전형 모오스 영역에 해당 도전형 고농도 불순물 이온과 확산방지용 제2불순물 이온을 주입하여 LDD 구조를 갖는 MOS FET를 형성하는 단계를 포함하여 이루어짐을 특징으로 하는 CMOS 소자 제조 방법.Forming a second conductive well on the first conductive semiconductor substrate to define the first and second conductive MOSFET regions, forming a gate oxide film and a field oxide film, forming a polycrystalline silicon layer on the entire surface, and then In order to prevent the diffusion of biconductive impurity ions into the channel region, the first pure ion implantation for diffusion prevention is injected into the polycrystalline silicon layer, and the conductive low concentration impurity ions are implanted into the first and second conductive moieties. Forming a gate sidewall of the gate, and implanting the conductive high concentration impurity ions and diffusion preventing second impurity ions into the first and second conductive MOS regions to form a MOS FET having an LDD structure. CMOS device manufacturing method comprising the. 제4항에 있어서, 상기 확산방지용 제1불순물 이온은 니트로겐을 포함함을 특징으로 하는 CMOS 소자 제조 방법.The method of claim 4, wherein the diffusion preventing first impurity ion comprises nitrogen. 제4항에 있어서, 상기 확산방지용 제2불순물 이온은 게르마늄 이온을 포함함을 특징으로 하는 CMOS 소자 제조 방법.The method of claim 4, wherein the second impurity ions for preventing diffusion include germanium ions. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950046374A 1995-12-04 1995-12-04 Method of manufacturing cmos device KR100192518B1 (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100402381B1 (en) * 2001-02-09 2003-10-17 삼성전자주식회사 Cmos transistor having germanium-contained policrystalline silicon gate and method of forming the same
KR100431812B1 (en) * 2001-12-29 2004-05-17 주식회사 하이닉스반도체 Method for forming poly gate electrode of semiconductor device

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100680436B1 (en) * 2000-12-08 2007-02-08 주식회사 하이닉스반도체 Method of manufacturing a transistor in a semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100402381B1 (en) * 2001-02-09 2003-10-17 삼성전자주식회사 Cmos transistor having germanium-contained policrystalline silicon gate and method of forming the same
KR100431812B1 (en) * 2001-12-29 2004-05-17 주식회사 하이닉스반도체 Method for forming poly gate electrode of semiconductor device

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