KR100192518B1 - Method of manufacturing cmos device - Google Patents
Method of manufacturing cmos device Download PDFInfo
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- KR100192518B1 KR100192518B1 KR1019950046374A KR19950046374A KR100192518B1 KR 100192518 B1 KR100192518 B1 KR 100192518B1 KR 1019950046374 A KR1019950046374 A KR 1019950046374A KR 19950046374 A KR19950046374 A KR 19950046374A KR 100192518 B1 KR100192518 B1 KR 100192518B1
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- polysilicon layer
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 21
- 239000012535 impurity Substances 0.000 claims abstract description 57
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 36
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims abstract description 30
- 239000000758 substrate Substances 0.000 claims abstract description 19
- 229910052732 germanium Inorganic materials 0.000 claims abstract description 17
- 229910052757 nitrogen Inorganic materials 0.000 claims abstract description 17
- -1 boron ion Chemical class 0.000 claims abstract description 15
- 239000004065 semiconductor Substances 0.000 claims abstract description 14
- 150000002500 ions Chemical class 0.000 claims description 32
- 229920005591 polysilicon Polymers 0.000 claims description 30
- CWGBFIRHYJNILV-UHFFFAOYSA-N (1,4-diphenyl-1,2,4-triazol-4-ium-3-yl)-phenylazanide Chemical compound C=1C=CC=CC=1[N-]C1=NN(C=2C=CC=CC=2)C=[N+]1C1=CC=CC=C1 CWGBFIRHYJNILV-UHFFFAOYSA-N 0.000 claims 1
- 238000000034 method Methods 0.000 abstract description 18
- 229910052796 boron Inorganic materials 0.000 abstract description 9
- 238000009792 diffusion process Methods 0.000 abstract description 6
- 230000009977 dual effect Effects 0.000 abstract description 5
- 229920002120 photoresistant polymer Polymers 0.000 description 16
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 9
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 6
- 238000005468 ion implantation Methods 0.000 description 6
- 238000002513 implantation Methods 0.000 description 4
- 238000000206 photolithography Methods 0.000 description 3
- 239000010936 titanium Substances 0.000 description 3
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 238000002844 melting Methods 0.000 description 2
- 230000008018 melting Effects 0.000 description 2
- 229910021332 silicide Inorganic materials 0.000 description 2
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- 229910021341 titanium silicide Inorganic materials 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910008484 TiSi Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
- H01L21/823842—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
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Abstract
본 발명은 CMOS소자 제조방법에 관한 것으로 듀얼(Dual) 게이트 CMOS소자에 있어서, 게이트 폴리에 이온주입된 보론이 채널영역으로 확산되는 것을 방지함과 동시에 게이트의 시트저항을 감소시키는데 적당한 CMOS소자 제조방법을 제공하기 위한 것으로써, 제1도전형 반도체 기판에 제2도 전형웰을 형성하여 제1, 제2도전형 모오스 영역을 정의한 후, 게이트 산화막과 필드 산화막을 형성하는 단계, 상기 기판 전면에 언도프 다결정 실리콘층을 형성한 후, 니트로겐과 게르마늄 이온을 동시에 상기 다결정 실리콘층에 도핑시키는 단계, 상기 다결정실리콘층을 선택적으로 제거하여 제1, 제2게이트 전극을 형성하는 단계, 상기 제1, 제2도전형 모오스 영역에 각각 해당 도전형의 저농도 불순물을 주입한 후, 상기 각각의 게이트 전극 양측면에 측벽을 형성하는 단계, 상기 제1, 제2도전형 모오스 영역에 각각 해당 도전형의 소오스/드레인용 고농도 불순물을 주입하는 단계를 포함하여 이루어짐을 특징으로 한다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a CMOS device, wherein in a dual gate CMOS device, a method for manufacturing a CMOS device suitable for preventing diffusion of boron ion implanted into a gate poly into a channel region and at the same time reducing sheet resistance of the gate. By providing a second conductive type well on the first conductive semiconductor substrate to define the first and second conductive MOS region, and forming a gate oxide and a field oxide film, the frozen on the entire surface of the substrate Forming a dope polycrystalline silicon layer, and then simultaneously doping nitrogen and germanium ions to the polycrystalline silicon layer, selectively removing the polycrystalline silicon layer to form first and second gate electrodes, After injecting low-concentration impurities of the corresponding conductivity type into the second conductive mode region, the sidewalls are formed on both sides of the respective gate electrodes. Characterized the yirueojim including the step of each implanting source / drain high-concentration impurity of the conductivity type in the first and second conductivity type regions Mohs.
Description
제1a~f도는 종래의 CMOS소자 제조방법을 나타낸 공정단면도.1A to F are process cross-sectional views showing a conventional CMOS device manufacturing method.
제2a~h도는 본 발명의 제1 실시예에 따른 CMOS소자 제조방법을 나타낸 공정단면도.2A to 2H are cross-sectional views illustrating a method of fabricating a CMOS device according to a first embodiment of the present invention.
제3a~f도는 본 발명의 제2 실시예에 따른 CMOS소자 제조방법을 나타낸 공정단면도.3A to 3F are process cross-sectional views showing a method of manufacturing a CMOS device according to a second embodiment of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
21 : n형 기판 22 : P형 웰21: n-type substrate 22: P-type well
23 : 산화막 24 : 필드산화막23: oxide film 24: field oxide film
25 : 다결정 실리콘 26a,26b : 제1, 제2게이트 전극25 polycrystalline silicon 26a, 26b first and second gate electrodes
27,29,32,33 : 제2, 제3, 제4, 제5감광막27,29,32,33: 2nd, 3rd, 4th, 5th photosensitive film
28a,28b : 저농도 n형 소오스/드레인 불순물 영역28a, 28b: low concentration n-type source / drain impurity region
30a,30b : 고농도 n형 소오스/드레인 불순물 영역30a, 30b: High concentration n-type source / drain impurity region
31a,31b : 게이트 측벽31a, 31b: gate sidewalls
본 발명은 반도체 소자의 제조방법에 관한 것으로 특히, 듀얼(Dual) 게이트 씨모오스(CMOS) 소자에 있어서, 게이트폴리에 이온주입된 보론(Boron)이 채널영역으로 확산되는 것을 방지하는데 적당한 씨모오스 소자 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device. In particular, in a dual gate CMOS device, a CMOS device suitable for preventing diffusion of boron ions implanted into the gate poly into a channel region is preferred. It relates to a manufacturing method.
일반적으로 CMOS소자는 p채널 MOS FET와 n채널 MOS FET를 하나의 칩에 구성하여 상보동작(Complementary) 시키도록 한 것이다.In general, a CMOS device is composed of a p-channel MOS FET and an n-channel MOS FET on a single chip to perform complementary operation.
상기 CMOS 소자는 이온주입(Ion Implatation) 기술의 실용화로 가능해졌으며, 소비전력이 낮고 바이폴라(Bipolar) 소자에 가까운 고속동작이 가능하여 메가비트급이 주류를 이루고 있다.The CMOS device has been made possible by the practical use of ion implantation technology, and low power consumption and high-speed operation close to a bipolar device makes the megabit class mainstream.
이하, 첨부도면을 참조하여 종래의 CMOS소자 제조방법을 설명하면 다음과 같다.Hereinafter, a conventional CMOS device manufacturing method will be described with reference to the accompanying drawings.
제1a~f도는 종래의 CMOS소자 제조방법을 나타낸 공정단면도이다.1A to F are process cross-sectional views showing a conventional CMOS device manufacturing method.
먼저, 제1a도에 도시한 바와 같이, n형 반도체 기판(1)의 소정영역에 p형 불순물 확산에 의해 P형 웰(2)을 형성하고, 이어서 게이트 산화막(3)과 필드 산화막(4)을 형성한다. 상기 필드 산화막(4)을 포함한 기판 전면에 게이트 전극용 폴리 실리콘층(5)을 형성하고, 상기 폴리 실리콘층(5)에 니트로겐(Nitrogen) 이온주입을 실시한다.First, as shown in FIG. 1A, the P-type well 2 is formed in a predetermined region of the n-type semiconductor substrate 1 by p-type impurity diffusion, and then the gate oxide film 3 and the field oxide film 4 are formed. To form. A gate electrode polysilicon layer 5 is formed on the entire substrate including the field oxide film 4, and nitrogen ion implantation is performed on the polysilicon layer 5.
이어, 제1b도에 도시한 바와 같이, 상기 폴리실리콘층(5) 상부에 제1감광막(도시하지 않음)을 도포하여 사진 식각공정을 통해 제1, 제2게이트 전극(5a)(5b)을 패터닝한 후, PMOS영역(즉, 제2게이트 전극 및 양쪽의 활성영역)에는 저농도 n형 불순물 이온이 주입되지 않도록 제2감광막(6)을 도포한다.Subsequently, as shown in FIG. 1B, a first photoresist film (not shown) is coated on the polysilicon layer 5 to form the first and second gate electrodes 5a and 5b through a photolithography process. After patterning, a second photosensitive film 6 is applied to the PMOS region (ie, the second gate electrode and both active regions) so that low concentration n-type impurity ions are not implanted.
그리고 상기 제1게이트 전극(5a)을 마스크로 이용하여 저농도 n형 불순물 이온(As)을 주입하므로써, 저농도 n형 소오스/드레인 불순물 영역(7a)7b)을 형성한다.The low concentration n-type impurity ions As are implanted using the first gate electrode 5a as a mask to form the low concentration n-type source / drain impurity regions 7a and 7b.
이어서, 제1c도에 도시된 바와 같이, 상기 제2감광막(6)을 제거하고 NMOS영역(즉, 제1게이트 전극 및 양측의 저농도 n형 소오스/드레인 불순물 영역(7a)(7b))상에 제3감광막(8)을 도포한 후, 상기 제2게이트 전극(5b)을 마스크로 이용하여 저농도 p형 불순물 이온(BF2)과 니트로겐 이온을 동시에 이온주입한다.Subsequently, as shown in FIG. 1C, the second photoresist film 6 is removed and on the NMOS region (i.e., the first gate electrode and the low concentration n-type source / drain impurity regions 7a and 7b on both sides). After the third photoresist film 8 is applied, low concentration p-type impurity ions BF 2 and nitrogen ions are ion implanted simultaneously using the second gate electrode 5b as a mask.
따라서 니트로겐 이온이 주입된 저농도 p형 소오스/드레인 불순물 영역(9a)(9b)이 형성된다.Therefore, low concentration p-type source / drain impurity regions 9a and 9b into which nitrogen ions are implanted are formed.
상기 제2게이트 전극(5b)은 니트로겐 이온이 주입된 p형 폴리 실리콘이된다.The second gate electrode 5b is p-type polysilicon implanted with nitrogen ions.
이어서 제1d도에 도시한 바와 같이, 상기 제3감광막(8)을 제거한 후, 제1, 제2게이트 측벽(10a)(10b)을 형성하고, 상기 제1게이트 전극(5a)상부와 p형 웰(2)영역의 n형 소오스/드레인 불순물 영역상에 고융점 금속인 티타늄(Ti)층을 형성하고, 아울러 제2게이트 전극(5b) 상부와 n형 반도체 기판(1)의 p형 소오스/드레인 불순물 영역상에 상기와 마찬가지로 고융점 금속인 티타늄층을 형성한 후, 열처리하면 저저항의 티타늄 실리사이드층(11)이 형성된다.Subsequently, as shown in FIG. 1D, after the third photosensitive film 8 is removed, first and second gate sidewalls 10a and 10b are formed, and the upper portion of the first gate electrode 5a and the p-type are formed. A high melting point titanium (Ti) layer is formed on the n-type source / drain impurity region of the well 2 region, and is formed on top of the second gate electrode 5b and the p-type source / of the n-type semiconductor substrate 1. As described above, a titanium layer, which is a high melting point metal, is formed on the drain impurity region and then heat treated to form a titanium silicide layer 11 having a low resistance.
다시 말해서, 상기 저저항 티타늄 실리사이드(TiSi2)층(11)은 다결정 폴리실리콘과 불순물 확산층 실리콘상에만 형성된다. 이어서, 상기 PMOS 영역상에 제4감광막(12)을 도포하고, 상기 제1게이트 전극(5a) 및 측벽(10a)을 마스크로 이용하여 고농도의 n형 불순물 이온(P)을 주입하면 LDD(Lightly Doped Drain) 구조를 갖는 NMOS FET가 형성된다. 또한, 제1e도에 도시한 바와 같이, 상기 제4감광막(12)을 제거한 후, NMOS영역상에 제5감광막(13)을 도포하고, 상기 제2게이트 전극(5b) 및 측벽(10b)을 마스크로 이용하여 고농도의 p형 불순물 이온을 주입하여 LDD구조를 갖는 PMOS FET가 형성된다.In other words, the low resistance titanium silicide (TiSi 2 ) layer 11 is formed only on the polycrystalline polysilicon and the impurity diffusion layer silicon. Subsequently, a fourth photoresist layer 12 is coated on the PMOS region, and a high concentration of n-type impurity ions P is implanted using the first gate electrode 5a and the sidewall 10a as a mask to lightly LDD (Lightly). An NMOS FET having a doped drain structure is formed. In addition, as shown in FIG. 1E, after the fourth photosensitive film 12 is removed, the fifth photosensitive film 13 is coated on the NMOS region, and the second gate electrode 5b and the sidewall 10b are removed. PMOS FETs having an LDD structure are formed by implanting high concentrations of p-type impurity ions using a mask.
이어서, 제1f도에 도시한 바와 같이, 상기 제5감광막(13)을 제거하면 종래의 듀얼 게이트 CMOS소자가 형성된다. 그러나 상기와 같은 종래의 CMOS소자 제조방법은 게이트 전극용 폴리실리콘층에 니티로겐 이온이 주입되므로 저항이 증가하게 된다. 따라서, 상기 저항을 감소시키기 위해 실리사이드 공정을 수행하여야 하는 문제점이 있었다.Subsequently, as shown in FIG. 1F, when the fifth photosensitive film 13 is removed, a conventional dual gate CMOS device is formed. However, in the conventional CMOS device manufacturing method as described above, the resistance is increased since nitigen ions are injected into the polysilicon layer for the gate electrode. Therefore, there is a problem that the silicide process must be performed to reduce the resistance.
본 발명은 상기의 문제점을 해결하기 위해 안출한 것으로, 니트로겐과 함께 게르마늄 이온을 주입하여 보론(Boron)이 채널영역으로 확산되는 것을 방지함과 동시에 게이트 전극의 시트(sheet) 저항을 감소시키는데 적당한 씨모스 소자 제조방법을 제공하는데 그 목적이 있다.The present invention has been made to solve the above problems, and is suitable for reducing the sheet resistance of the gate electrode while preventing the diffusion of boron into the channel region by injecting germanium ions with nitrogen. It is an object to provide a CMOS device manufacturing method.
상기의 목적을 달성하기 위한 본 발명의 CMOS소자 제조방법은 제1도전형 반도체 기판에 제2도전형 웰을 형성하여 제1, 제2도전형 모오스 영역을 정의한 후, 게이트 산화막과 필드 산화막을 형성하는 단계, 상기 기판 전면에 언도프 다결정실리콘층을 형성한 후, 니트로겐과 게르마늄 이온을 동시에 상기 다결정실리콘층에 도핑시키는 단계, 상기 다결정실리콘층을 선택적으로 제거하여 제1, 제2게이트 전극을 형성하는 단계, 상기 제1, 제2도전형 모오스 영역에 각각 해당 도전형의 저농도 불순물을 주입한 후, 상기 각각의 게이트 전극 양측면에 측벽을 형성하는 단계, 상기 제1, 제2도전형 모오스 영역에 각각 해당 도전형의 소오스/드레인용 고농도 불순물을 주입하는 단계를 포함하여 이루어지고, 본 발명의 다른 실시예에 따른 반도체 소자 제조방법은 제1 도전형 반도체 기판에 제2도전형 웰을 형성하여 제1, 제2도전형 모오스 영역을 정의 한 후, 게이트 산화막 및 필드 산화막을 형성하는 단계, 상기 기판 전면에 언도프 다결정실리콘층을 형성한 후, 니트로겐을 상기 다결정실리콘층에 도핑시키는 단계, 상기 다결정실리콘층을 선택적으로 제거하여 제1, 제2게이트 전극을 형성하는 단계, 상기 제1, 제2도전형 모오스 영역에 각각 해당 도전형의 저농도 불순물을 주입한 후, 각각의 게이트 전극 양측면에 측벽을 형성하는 단계, 상기 제1, 제2도전형의 모오스 영역에 각각 게르마늄 이온과 고농도의 소오스/드레인용 불순물 이온을 동시에 주입하는 단계를 포함하여 이루어짐을 특징으로 한다.In the CMOS device fabrication method of the present invention for achieving the above object, the second conductive well is formed on the first conductive semiconductor substrate to define the first and second conductive MOS regions, and then the gate oxide film and the field oxide film are formed. And forming an undoped polysilicon layer on the entire surface of the substrate, and then simultaneously doping the polycrystalline silicon layer with nitrogen and germanium ions, and selectively removing the polysilicon layer to remove the first and second gate electrodes. Forming, injecting low-concentration impurities of a corresponding conductivity type into the first and second conductivity-type MOS regions, respectively, and forming sidewalls on both sides of each gate electrode, and forming the first and second conductivity-type MOS regions. Injecting a high-concentration impurity for the source / drain of the conductive type, respectively, in the semiconductor device manufacturing method according to another embodiment of the present invention After forming a second conductive well in the conductive semiconductor substrate to define the first and second conductive mos region, forming a gate oxide film and a field oxide film, after forming an undoped polysilicon layer on the entire surface of the substrate And doping nitrogen into the polysilicon layer, selectively removing the polysilicon layer to form first and second gate electrodes, and corresponding conductive types in the first and second conductive MOS regions, respectively. After implanting the low concentration impurity, forming sidewalls on both sides of each gate electrode, and simultaneously implanting germanium ions and high concentration source / drain impurity ions into the first and second conductivity type moss regions, respectively. Characterized in that made.
이하, 첨부된 도면을 참조하여 본 발명의 CMOS소자 제조방법을 설명하면 다음과 같다.Hereinafter, a CMOS device manufacturing method of the present invention will be described with reference to the accompanying drawings.
제2a~h도는 본 발명의 제1 실시예에 따른 CMOS소자 제조방법을 나타낸 공정단면도이다.2A to H are cross-sectional views illustrating a method of fabricating a CMOS device according to a first embodiment of the present invention.
먼저, 본 발명의 제1 실시예에 따른 CMOS소자 제조방법은 제2a도에 도시된 바와 같이, n형 반도체 기판(21)의 NMOS FET가 형성될 부위에 p형 불순물을 확산시켜 p형 웰(22)을 형성한 후, 게이트 산화막(23)과 필드 산화막(24)을 형성한다.First, in the CMOS device fabrication method according to the first embodiment of the present invention, as shown in FIG. 2A, the p-type impurity is diffused to the region where the NMOS FET of the n-type semiconductor substrate 21 is to be formed. After the 22 is formed, the gate oxide film 23 and the field oxide film 24 are formed.
이어, 제2b도에 도시한 바와 같이, 필드 산화막(24)을 포함한 게이트 산화막(23) 전면에 불순물이 도핑되지 않은 폴리실리콘층(25)을 형성한 후, 상기 폴리실리콘층(25) 상부에 게르마늄(Germanium)과 니트로겐(Nitrogen)을 이온주입 한다.Subsequently, as shown in FIG. 2B, the polysilicon layer 25 without impurities is formed on the entire surface of the gate oxide layer 23 including the field oxide layer 24, and then on the polysilicon layer 25. Germanium and Nitrogen are ion implanted.
이어, 제2c도에 도시한 바와 같이, 상기 폴리 실리콘층(25) 상부에 제1감광막(도시하지 않음)을 도포하여 사진 식각공정을 통해 제1, 제2게이트 전극(26a)(26b)을 패터닝한다.Subsequently, as shown in FIG. 2C, a first photoresist film (not shown) is coated on the polysilicon layer 25 to form the first and second gate electrodes 26a and 26b through a photolithography process. Pattern.
이어, 제2d도에 도시한 바와 같이, PMOS영역(즉, 상기 제2게이트 전극(26b) 및 양측의 활성영역)에는 n형 불순물이 주입되지 않도록 제2감광막(27)을 도포하고, 상기 제1게이트 전극(26a)을 마스크로 이용하여 저농도 n형 불순물 이온(As)을 주입하므로써, 제1게이트 전극(26a) 양측의 p형 웰(22)에 저농도의 n형 소오스/드레인 불순물 영역(28a)(28b)을 형성한다.Subsequently, as shown in FIG. 2D, a second photosensitive film 27 is coated on the PMOS region (that is, the second gate electrode 26b and the active regions on both sides) so that n-type impurities are not injected. The low concentration n-type source / drain impurity region 28a is injected into the p-type well 22 on both sides of the first gate electrode 26a by implanting the low concentration n-type impurity ions As using the one gate electrode 26a as a mask. ) 28b.
이어서, 제2e도에 도시한 바와 같이, 상기 제2감광막(27)을 제거한 후, NMOS영역(즉, 제1게이트 전극(26a) 및 저농도 n형 소오스/드레인 불순물 영역(28a)(28b))에는 p형 불순물 이온이 주입되지 않도록 상기 NMOS영역상에 제3감광막(29)을 도포한다. 그리고, 상기 제2게이트 전극(26b)을 마스크로 이용하여 저농도의 p형 불순물 이온(FB2)을 주입하므로써, 제2게이트 전극(26b) 양측의 n형 반도체 기판(21)에 저농도 p형 소오스/드레인 불순물 영역(30a)(30b)을 형성한다. 이때, 상기 제1, 제2게이트 전극(26a)(26b)용 폴리실리콘층에 이온주입된 니트로겐은 후속 열처리 공정시, 게르마늄에 의해 게이트 산화막(23)과 n형 반도체 기판(21)의 계면으로 확산되고, 상기 확산되는 니트로겐에 의해 상기 p형 불순물 이온인 보론(Boron)이 채널영역으로 확산되는 것을 방지한다.Subsequently, as shown in FIG. 2E, after removing the second photosensitive film 27, the NMOS region (i.e., the first gate electrode 26a and the low concentration n-type source / drain impurity regions 28a and 28b). The third photosensitive film 29 is coated on the NMOS region so as not to implant p-type impurity ions. The low concentration p-type source is implanted into the n-type semiconductor substrate 21 on both sides of the second gate electrode 26b by implanting low concentration p-type impurity ions FB 2 using the second gate electrode 26b as a mask. Drain impurity regions 30a and 30b are formed. In this case, the nitrogen ion-implanted into the polysilicon layers for the first and second gate electrodes 26a and 26b is an interface between the gate oxide film 23 and the n-type semiconductor substrate 21 by germanium in a subsequent heat treatment process. The boron, which is the p-type impurity ion, is prevented from being diffused into the channel region by the diffused nitrogen.
또한, 상기 게르마늄은 폴리실리콘에 고농도로 존재할 때, 시트 저항을 감소시킨다. 즉, 니트로겐과 게르마늄을 동시에 폴리실리콘층에 도핑할 경우, 상기 폴리실리콘층에는 데미지가 발생하여 이후에 열처리 공정을 수행하면 보론입자들이 데미지를 입은 폴리실리콘층으로 몰리게 되어 보론이 채널영역으로 확산되는 것을 방지할 수가 있다.In addition, the germanium reduces the sheet resistance when present in high concentration in polysilicon. That is, when doping nitrogen and germanium at the same time to the polysilicon layer, damage occurs to the polysilicon layer, and when the heat treatment is performed later, the boron particles are driven to the damaged polysilicon layer, and boron diffuses into the channel region Can be prevented.
여기서, 게르마늄이 니트로겐과 함께 보론의 확산을 방지하는 역할만을 수행하는 것이 아니라 전술한 바와 같이, 폴리실리콘의 시트 저항을 감소시키는 역할도 수행하기 때문에 실리사이드 공정이 필요치 않게 된다.Here, since the germanium does not only play a role of preventing diffusion of boron together with nitrogen, but also plays a role of reducing sheet resistance of polysilicon as described above, a silicide process is not necessary.
이어, 제2f도에 도시한 바와 같이, 상기 제3감광막(29)을 제거한 후, 전면에 절연막을 증착하여 제1, 제2게이트 전극(26a)(26b)의 측벽(31a)(31b)을 형성한 후, PMOS영역상에 제4감광막(32)을 도포하여 고농도 n형 불순물 이온주입시 상기 n형 불순물 이온의 PMOS영역으로의 주입을 방지하도록 한다.Subsequently, as shown in FIG. 2F, after the third photoresist layer 29 is removed, an insulating film is deposited on the entire surface to form sidewalls 31a and 31b of the first and second gate electrodes 26a and 26b. After the formation, the fourth photosensitive film 32 is coated on the PMOS region to prevent the implantation of the n-type impurity ions into the PMOS region during the implantation of high concentration n-type impurity ions.
이어, 상기 제1게이트 전극(26a) 및 측벽(31a)을 마스크로 이용하여 고농도의 n형 불순물 이온을 주입하므로써, LDD구조를 갖는 NMOS FET를 형성한다. 이때, 상기 제1게이트 전극(26a)용 폴리 실리콘에는 n형 불순물 이온이 주입되어 n형 폴리 게이트가 된다.Subsequently, a high concentration of n-type impurity ions are implanted using the first gate electrode 26a and the sidewall 31a as a mask to form an NMOS FET having an LDD structure. In this case, n-type impurity ions are implanted into the polysilicon for the first gate electrode 26a to form an n-type poly gate.
이어서, 제2g도에 도시한 바와 같이, 제4감광막(32)을 제거한 후, 상기 NMOS영역상에 제5감광막(33)을 도포하여 고농도 p형 불순물 이온주입시 상기 NMOS영역으로 주입되지 않도록 한다.Subsequently, as shown in FIG. 2G, after the fourth photoresist film 32 is removed, the fifth photoresist film 33 is coated on the NMOS region so as not to be implanted into the NMOS region during the implantation of high concentration p-type impurity ions. .
이어, 상기 제2게이트 전극(26b) 측벽(31b)을 마스크로하여, 고농도의 p형 불순물 이온을 주입하므로써, LDD구조를 갖는 PMOS FET를 형성한다. 이때, 상기 제2게이트 전극(26b)을 폴리 실리콘에서 p형 불순물 이온이 주입되어 p형 폴리 게이트가 된다.Subsequently, a high concentration of p-type impurity ions are implanted using the sidewall 31b of the second gate electrode 26b as a mask to form a PMOS FET having an LDD structure. At this time, p-type impurity ions are implanted into the second gate electrode 26b from polysilicon to become a p-type poly gate.
결과적으로 제2h도에 도시한 바와 같이, 상기 제5감광막(33)을 제거하면 듀얼(Dual) 게이트 CMOS FET가 형성된다.As a result, as shown in FIG. 2H, when the fifth photosensitive film 33 is removed, a dual gate CMOS FET is formed.
한편, 제3a~f도는 본 발명의 제2 실시예에 따른 CMOS소자 제조방법을 나타낸 공정단면도이다.3A to 3F are cross-sectional views illustrating a method of manufacturing a CMOS device according to a second exemplary embodiment of the present invention.
상기 방법은 게이트 산화막상에 증착된 게이트 전극용 폴리 실리콘층에 니트로겐(Nitrogen)만 주입하고, 게르마늄은 게이트 측벽을 이용한 고농도의 불순물 이온주입시 동시에 주입하는 방법이다. 즉, 제3a도에 도시한 바와 같이, n형 반도체 기판(41)의 NMOS FET가 형성될 부위에 p형 불순물을 확산시켜 p형 웰(42)을 형성한 후, 게이트 산화막(43)과 필드 산화막(44)을 형성한다.The above method is a method of implanting only nitrogen into the polysilicon layer for the gate electrode deposited on the gate oxide layer, and germanium is implanted at the same time when a high concentration of impurity ions are implanted using the gate sidewall. That is, as shown in FIG. 3A, after forming the p-type well 42 by diffusing the p-type impurity in the portion where the NMOS FET of the n-type semiconductor substrate 41 is to be formed, the gate oxide film 43 and the field are formed. An oxide film 44 is formed.
상기 필드 산화막(44)을 포함한 전면에 게이트 전극을 형성하기 위해 불순물이 도핑되지 않은 폴리 실리콘층을 증착한 후, 상기 폴리 실리콘층에 니트로겐 이온을 주입하고, 제1감광막(도시하지 않음)을 도포하여 사진 식각 공정을 통해 제1, 제2게이트 전극(45a)(45b)을 형성한다.After depositing a polysilicon layer not doped with impurities to form a gate electrode on the front surface including the field oxide layer 44, nitrogen ions are implanted into the polysilicon layer, and a first photoresist layer (not shown) is formed. By coating, the first and second gate electrodes 45a and 45b are formed through a photolithography process.
이어서, 제3b도에 도시한 바와 같이, PMOS영역(즉, 제2게이트 전극 및 양측의 활성영역)에는 n형 불순물 이온이 주입되지 않도록 제2감광막(46)을 도포한 후, 상기 NMOS영역의 제1게이트 전극(45a)을 마스크로 이용하여 저농도 n형 불순물 이온(As)을 주입하여 제1게이트 전극(45a) 양측의 p형 웰(42)에 저농도의 n형 소오스/드레인 불순물 영역(47a)(47b)을 형성한다.Subsequently, as shown in FIG. 3B, the second photosensitive film 46 is coated so that n-type impurity ions are not implanted into the PMOS region (i.e., the second gate electrode and the active region on both sides), and then the Low concentration n-type impurity ions As are implanted using the first gate electrode 45a as a mask, and the low concentration n-type source / drain impurity region 47a is formed in the p-type wells 42 on both sides of the first gate electrode 45a. ) 47b.
이어, 제3c도에 도시한 바와 같이, 상기 제2감광막(46)을 제거한 후, 상기 NMOS영역(즉, 제1게이트전극 및 저농도의 n형 소오스/드레인 불순물 영역)에는 p형 불순물이 주입되지 않도록 상기 NMOS영역상에 제3감광막(48)을 도포한다. 이어서, 상기 제2게이트 전극(45a)을 마스크로 이용하여 저농도 p형 불순물 이온(BF2)을 주입하여 상기 제2게이트 전극(45a) 양측의 n형 반도체 기판(41)에 저농도의 p형 소오스/드레인 불순물 영역(49a)(49b)을 형성한다.Subsequently, as shown in FIG. 3C, after removing the second photoresist layer 46, p-type impurities are not implanted into the NMOS region (ie, the first gate electrode and the low concentration n-type source / drain impurity region). The third photoresist film 48 is coated on the NMOS region so as to prevent damage. Subsequently, a low concentration p-type impurity ion (BF 2 ) is implanted using the second gate electrode 45a as a mask, and a low concentration p-type source is implanted into the n-type semiconductor substrate 41 on both sides of the second gate electrode 45a. Drain impurity regions 49a and 49b are formed.
이어서, 제3d도에 도시한 바와 같이, 제3감광막(48)을 제거하고, 전면에 절연막을 증착하여 에치백(etch back) 공정을 통해 제1, 제2게이트 전극(45a)(45b)의 측벽(50a)(50b)을 형성한 후, 상기 PMOS영역상에 제4감광막(51)을 도포하여 고농도 n형 부순물 이온주입시 상기 PMOS영역에 n형 불순물 이온이 주입되지 않도록 한다. 이어서, 상기 제1게이트 전극(45a) 및 측벽(50a)을 마스크로 이용하여 고농도의 n형 불순물 이온과 게르마늄(Ge) 이온을 동시에 주입하여 LDD구조를 갖는 NMOS FET를 형성한다.Subsequently, as shown in FIG. 3D, the third photoresist film 48 is removed, an insulating film is deposited on the entire surface, and an etch back process is performed to etch back the first and second gate electrodes 45a and 45b. After the sidewalls 50a and 50b are formed, a fourth photoresist film 51 is coated on the PMOS region so that n-type impurity ions are not implanted into the PMOS region during high concentration n-type impurity ion implantation. Subsequently, a high concentration of n-type impurity ions and germanium (Ge) ions are simultaneously implanted using the first gate electrode 45a and the sidewall 50a as a mask to form an NMOS FET having an LDD structure.
이어, 상기 제4감광막(51)을 제거한 후, 제3c도에 도시한 바와 같이, 상기 NMOS영역상에 제5감광막(52)을 도포하여 고농도의 p형 불순물 이온이 상기 NMOS영역에 주입되지 않도록 한다.Subsequently, after the fourth photoresist film 51 is removed, a fifth photoresist film 52 is coated on the NMOS region, as shown in FIG. 3C, so that a high concentration of p-type impurity ions are not injected into the NMOS region. do.
그리고 상기 제2게이트 전극(45b) 및 측벽(50b)을 마스크로 이용하여 고농도의 p형 불순물 이온과 게르마늄 이온을 동시에 주입하여 LDD구조를 갖는 PMOS FET를 형성한다. 이어서, 상기 제5감광막을 제거하면 제3f도에 도시한 바와 같이, 듀얼(Dual) 게이트 CMOS가 형성된다. 여기서, 상기 고농도의 불순물 이온주입과 동시에 주입하는 게르마늄 이온은 상기 게르마늄 이온주입에 따른 이온주입 농도분포의 끝부분이 이온 주입에 의한 손상(damage)로 인해 보론(borom)이 채널영역으로 확산되는 것을 방지한다.A high concentration of p-type impurity ions and germanium ions are simultaneously implanted using the second gate electrode 45b and the sidewall 50b as a mask to form a PMOS FET having an LDD structure. Subsequently, when the fifth photoresist film is removed, as shown in FIG. 3F, a dual gate CMOS is formed. Here, the germanium ions implanted at the same time as the implantation of the high concentration of impurity ions is that the boron is diffused into the channel region at the end of the ion implantation concentration distribution according to the germanium ion implantation. prevent.
이상 상술한 바와 같이, 본 발명의 CMOS소자 제조방법은 게이트 전극에 주입된 보론 이온이 채널쪽으로 확산되는 현상을 방지하고, 게르마늄으로 인해 게이트의 시트 저항을 감소시킨다. 또한, 얇은 소오스/드레인 영역이 형성 가능하며, 니트로겐에 의해 이온 주입에 따른 손상을 감소시키는 효과가 있다.As described above, the CMOS device fabrication method of the present invention prevents the boron ions injected into the gate electrode from diffusing toward the channel and reduces the sheet resistance of the gate due to germanium. In addition, a thin source / drain region can be formed, and the effect of reducing the damage caused by ion implantation by nitrogen can be obtained.
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| KR100431812B1 (en) * | 2001-12-29 | 2004-05-17 | 주식회사 하이닉스반도체 | Method for forming poly gate electrode of semiconductor device |
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