KR970053817A

KR970053817A - Semiconductor integrated circuit to eliminate electromagnetic interference

Info

Publication number: KR970053817A
Application number: KR1019950050713A
Authority: KR
Inventors: 이경익; 최종명
Original assignee: 김광호; 삼성전자 주식회사
Priority date: 1995-12-15
Filing date: 1995-12-15
Publication date: 1997-07-31

Abstract

1.청구범위에 기재된 발명이 속한 기술분야1. Technical field to which the invention described in the claims belongs

전자파 장해를 제거하기 위한 반도체 집적회로에 관한 것이다.The present invention relates to a semiconductor integrated circuit for removing electromagnetic interference.

2. 발명이 해결하려고 하는 기술적 과제2. The technical problem to be solved by the invention

전자파 장해를 제거하기 위한 반도체 집적회로를 제공함에 있다.Disclosed is a semiconductor integrated circuit for eliminating electromagnetic interference.

3. 발명의 해결방법의 요지3. Summary of Solution to Invention

집적회로 내에서 발생하는 전자파 장해인 방사 노이즈를 집적회로 내부에서 직접 제거하기 위한 회로에 있어서, 코아논리부인 CPU와, 칩 외부에서 상기 코아논리부에 전원을 제공하기 위한 제1, 2패드라인에 접속된 패드와, 상기 제1패드라인에 접속되고 제1, 2입출력포트를 서로 접속시키기 위한 제1, 2전원전송라인과, 상기 코아논리부 주변에 형성되고 상기 제2패드라인과 저항을 통해 접속되고 상기 코아논리부에 전원전압 및 접지전압을 제공하기 위한 제3, 4전원전송라인이 다수의 바이패스 또는 필터수단에 의해 서로 접속되는 것을 요지로한다.A circuit for directly eliminating radiation noise, which is an electromagnetic interference generated in an integrated circuit, in an integrated circuit, comprising: a CPU, which is a core logic unit, and first and second pad lines for supplying power to the core logic unit outside a chip. A pad connected to the first pad line, the first and second power supply lines for connecting the first and second input / output ports to each other, and formed around the core logic portion and through the second pad line and a resistor. The third and fourth power supply transmission lines are connected to each other by a plurality of bypass or filter means to be connected and to provide a power supply voltage and a ground voltage to the core logic unit.

4. 발명의 중요한 용도4. Important uses of the invention

전자파 장해를 제거하기 위한 반도체 집적회로에 적합하다.It is suitable for semiconductor integrated circuits for eliminating electromagnetic interference.

※ 선택도 : 제2도※ Selectivity: 2nd

Description

Semiconductor integrated circuit to eliminate electromagnetic interference

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 본 발명의 일 실시예에 따른 반도체 집적회로로 조합된 칩의 개략적인 내부구성을 보인 도면.2 is a schematic internal configuration of a chip combined into a semiconductor integrated circuit according to an embodiment of the present invention.

Claims

A method for eliminating electromagnetic interference in an integrated circuit comprising a core, a CPU, an input / output port, and a power transmission line for transmitting power to the core logic unit, the method comprising: transmitting power connected between the core logic unit and a pad; Forming a predetermined resistance in the line and forming a bypass capacitance between the power transmission lines so that noise generated in the core logic unit is not directly transmitted to the input / output port.

A circuit for directly eliminating radiation noise, which is an electromagnetic interference generated in an integrated circuit, in an integrated circuit, comprising: a CPU, which is a core logic unit, and a first pad line for supplying power to the core logic unit outside a chip. A connected pad; First and second power transmission lines connected to the first pad line and for connecting first and second input / output ports to each other; The third and fourth power transmission lines are formed around the core logic part and connected to the second pad line through a resistor and provide power voltage and ground voltage to the core logic part by a plurality of bypass or filter means. A circuit for removing radiation noise, characterized in that connected to each other.

3. The circuit of claim 2, wherein the degradation is about 100 ohms.

※ Note: The disclosure is based on the initial application.