JPH0575551A - Clock signal transmitting circuit - Google Patents

Abstract

PURPOSE:To reduce the radiation of a higher harmonic of an integer multiple as much as the clock signal frequency received from a clock transmission line. CONSTITUTION:The clock signals received through a clock signal output terminal of a clock signal generating circuit 11 are supplied to the clock signal input terminals of the clock signal passive circuits 13, 14 and 15 through a resistor 12. The resistor 12 is set at the prescribed resistance value so that the impedances of the clock signal transmission lines set between the resistor 12 and the circuits 13-15 respectively are coincident with the impedances of the clock signal input terminals of the circuits 13-15.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock signal transmission circuit used in automobile telephones and mobile telephones.

[0002]

2. Description of the Related Art Conventionally, a clock signal transmission circuit of this type is composed of a clock signal generation circuit, a clock signal passive circuit which operates by a clock signal output from the clock signal generation circuit, and a connecting line which directly connects these circuits. It consists of a clock transmission line.

[0003]

However, in the conventional clock signal transmission circuit, the output impedance of the clock signal generation circuit and the input impedance of the clock signal passive circuit do not match. For this reason, the clock signal frequency is distorted due to mismatch on the clock transmission line, and harmonics that are an integral multiple are generated and are radiated to the surroundings. There was a problem such as noise being generated in the device.

An object of the present invention is to solve this problem, and an object of the present invention is to provide an excellent clock signal transmission circuit capable of reducing radiation of harmonics that are an integral multiple of the clock signal frequency from the clock signal transmission line.

[0005]

In order to solve this object, a clock signal transmission circuit of the present invention comprises a clock signal generation circuit and a clock signal passive circuit which operates with a clock signal output from the clock signal generation circuit. A clock signal transmission line in which a resistor is arranged in series is provided between the clock signal output end of the clock signal generation circuit and the clock signal input end of the clock signal passive circuit.

[0006]

Therefore, according to the clock signal transmission circuit of the present invention, since the impedance of the clock transmission line and the input impedance of the clock signal passive circuit are matched by the resistor, it is an integral multiple of the clock signal frequency from the clock transmission line. It is possible to reduce the radiation of higher harmonic waves.

[0007]

Embodiments of a clock signal transmission circuit according to the present invention will be described below with reference to the drawings.

FIG. 1 shows the configuration of the embodiment. In FIG. 1, 11 is a clock signal generation circuit, and 12 is
It is a resistor whose one end is connected to the clock signal output terminal of the clock signal generation circuit 11. Reference numerals 13, 14, and 15 are clock signal passive circuits, respectively, and the other end of the resistor 12 is connected to each clock signal input end, and the clock signal from the clock signal generation circuit 11 is supplied. The resistor 12 is a clock signal passive circuit 13, 14,
Set to a value that matches the input impedance of 15.

The operation of the above configuration will be described. From the resistor 12 to the clock signal passive circuit 13, 14,
The impedance of the clock signal transmission line up to the respective clock signal input ends of 15 approaches the input impedance of the clock signal passive circuit, and the clock signal generation circuit 1
1 clock signal output terminal and clock signal passive circuit 1
The impedance between the clock signal input terminals 3, 14, and 15 can be matched.

As described above, since the impedance of the clock signal transmission line from the resistor 12 to the respective input ends of the clock signal passive circuits 13, 14, 15 approaches the input impedance of the clock signal passive circuit, the mismatch is prevented. As a result, radiation of harmonics that are an integral multiple of the frequency of the clock signal from the clock transmission line can be reduced, and adverse effects such as malfunction of circuits in the device and noise generation in surrounding equipment due to this unnecessary wave can be prevented.

In this embodiment, the clock signal is supplied to the three clock signal passive circuits 13, 14 and 15 through one resistor 12, but the present invention is not limited to this, and four or more clock signal passive circuits are provided. A clock signal may be supplied to the circuit, and a similar effect can be obtained even if a resistor is connected in series to each input terminal of the clock signal passive circuit. In this case, it suffices to dispose a resistor whose impedance is matched.

[0012]

As is apparent from the above description, in the clock signal transmission circuit of the present invention, the resistor is arranged in series with the clock transmission line, and the impedance of the clock transmission line and the clock signal passive circuit are provided by this resistor. Since the input impedance is matched with the input impedance, the radiation of harmonics that are an integral multiple of the clock signal frequency can be reduced.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a clock signal transmission circuit of the present invention.

[Explanation of symbols]

 11 Clock Signal Generation Circuit 12 Resistors 13, 14, 15 Clock Signal Passive Circuit

Claims (1)

[Claims] 1. A clock signal generation circuit, a clock signal passive circuit that operates with a clock signal output from the clock signal generation circuit, a clock signal output terminal of the clock signal generation circuit, and a clock signal of the clock signal passive circuit. A clock signal transmission circuit comprising a clock signal transmission line in which a resistor is arranged in series with an input end.