KR970053517A - Method of forming multilayer wiring structure of semiconductor device - Google Patents

Method of forming multilayer wiring structure of semiconductor device Download PDF

Info

Publication number
KR970053517A
KR970053517A KR1019950047399A KR19950047399A KR970053517A KR 970053517 A KR970053517 A KR 970053517A KR 1019950047399 A KR1019950047399 A KR 1019950047399A KR 19950047399 A KR19950047399 A KR 19950047399A KR 970053517 A KR970053517 A KR 970053517A
Authority
KR
South Korea
Prior art keywords
forming
substrate
wiring
insulating film
entire surface
Prior art date
Application number
KR1019950047399A
Other languages
Korean (ko)
Other versions
KR0172504B1 (en
Inventor
황준
Original Assignee
김주용
현대전자산업 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김주용, 현대전자산업 주식회사 filed Critical 김주용
Priority to KR1019950047399A priority Critical patent/KR0172504B1/en
Publication of KR970053517A publication Critical patent/KR970053517A/en
Application granted granted Critical
Publication of KR0172504B1 publication Critical patent/KR0172504B1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226—Via connections in a multilevel interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/76879—Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

본 발명은 반도체장치의 다층배선구조 형성방법에 관한 것으로, 상·하층 금속배선간의 접촉저항을 감소시키고 다층배선구조의 표면 평탄화를 이룰 수 있도록 한 것이다.The present invention relates to a method for forming a multi-layered wiring structure of a semiconductor device, and to reduce the contact resistance between the upper and lower metal wirings and to achieve a planarization of the surface of the multilayered wiring structure.

이를 위해 본 발명은 반도체기판상에 하층 금속배선을 형성하는 단계와, 상기 하층 금속배선이 형성된 기판 전면에 제1배선층간 절연막을 형성하는 단계, 상기 제1배선층간 절연막상에 포토레지스트를 도포하고 이를 선택적으로 노광 및 현상하여 소정의 비아 콘택홀이 형성될 위치에 포토레지스트패턴을 형성하는 단계, 기판 전면에 평탄화 절연층을 형성하여 표면을 평탄화시키는 단계, 상기 포토레지스트패턴을 제거하여 상기 평탄화 절연층 소정부분에 비아 콘택홀을 형성하는 단계, 기판 전면에 제2배선층간 절연막을 형성하는 단계, 상기 제2배선층간 절연막을 이방성 식각하여 상기 하층 금속배선을 노출시키는 단계, 기판 전면에 금속을 증착하고 소정패턴으로 패터닝하여 상기 비아 콘택홀을 통해 상기 하층 금속배선과 접속되는 상층 금속배선을 형성하는 단계로 이루어지는 반도체장치의 다층배선구조 형성방법을 제공한다.To this end, the present invention is to form a lower layer metal wiring on the semiconductor substrate, and to form a first wiring interlayer insulating film on the entire surface of the substrate on which the lower metal wiring is formed, applying a photoresist on the first wiring interlayer insulating film Selectively exposing and developing the photoresist pattern at a position where a predetermined via contact hole is to be formed, forming a planarization insulating layer on the entire surface of the substrate to planarize the surface, and removing the photoresist pattern to form the planarization insulation Forming a via contact hole in a predetermined portion of the layer, forming a second interlayer insulating film on the entire surface of the substrate, anisotropically etching the second interlayer insulating film to expose the lower metal wiring, and depositing a metal on the entire surface of the substrate An upper metal wiring connected to the lower metal wiring through the via contact hole by patterning a predetermined pattern To provide a multi-layer wiring structure forming a semiconductor device comprising the steps of forming.

Description

반도체장치의 다층배선구조 형성방법Method of forming multilayer wiring structure of semiconductor device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 본 발명에 의한 반도체장치의 다층배선구조 형성방법을 도시한 공정순서도이다.2 is a process flowchart showing a method for forming a multilayer wiring structure of a semiconductor device according to the present invention.

Claims (4)

반도체기판상에 하층 금속배선을 형성하는 단계와, 상기 하층 금속배선이 형성된 기판 전면에 제1배선층간 절연막을 형성하는 단계, 상기 제1배선층간 절연막상에 포토레지스트를 도포하고 이를 선택적으로 노광 및 현상하여 소정의 비아 콘택홀이 형성될 위치에 포토레지스트패턴을 형성하는 단계, 기판 전면에 평탄화 절연층을 형성하여 표면을 평탄화시키는 단계, 상기 포토레지스트패턴을 제거하여 상기 평탄화 절연층 소정부분에 비아 콘택홀을 형성하는 단계, 기판 전면에 제2배선층간 절연막을 형성하는 단계, 상기 제2배선층간 절연막을 이방성 식각하여 상기 하층 금속배선을 노출시키는 단계, 기판 전면에 금속을 증착하고 소정패턴으로 패터닝하여 상기 비아 콘택홀을 통해 상기 하층 금속배선과 접속되는 상층 금속배선을 형성하는 단계로 이루어지는 것을 특징으로 하는 반도체장치의 다층배선구조 형성방법.Forming a lower metal wiring on the semiconductor substrate, forming a first interlayer insulating film on the entire surface of the substrate on which the lower metal wiring is formed, applying a photoresist on the first wiring interlayer insulating film and selectively exposing the same; Developing to form a photoresist pattern at a position where a predetermined via contact hole is to be formed; forming a planarization insulating layer on the entire surface of the substrate to planarize the surface; removing the photoresist pattern to form a via in a predetermined portion of the planarization insulating layer Forming a contact hole, forming a second interlayer insulating film on the entire surface of the substrate, anisotropically etching the second interlayer insulating film, exposing the lower metal wiring, depositing a metal on the entire surface of the substrate, and patterning the pattern Forming an upper metal wiring connected to the lower metal wiring through the via contact hole A method for forming a multi-layered wiring structure of a semiconductor device, characterized by 제1항에 있어서, 상기 제1 및 제2배선층간 절연막은 1000-3000Å 정도의 얇은 두께로 형성하는 것을 특징으로 하는 반도체장치의 다층배선구조 형성방법.The method for forming a multilayer wiring structure of a semiconductor device according to claim 1, wherein the insulating film between the first and second wiring layers is formed to a thin thickness of about 1000-3000 Å. 제1항에 있어서, 상기 평탄화 절연층은 상기 포토레지스트패턴이 형성된 기판 전면에 SOG를 도포한 후, 이를 에치백하여 형성하는 것을 특징으로 하는 반도체장치의 다층배선구조 형성방법.The method of claim 1, wherein the planarization insulating layer is formed by coating SOG on the entire surface of the substrate on which the photoresist pattern is formed and then etching back the SOG. 제1항에 있어서, 상기 평탄화 절연층은 포토레지스트가 없는 부분에만 선택적으로 증착되는 액상 절연물질(LPD)을 증착하여 형성하는 것을 특징으로 하는 반도체장치의 다층배선구조 형성방법.The method of claim 1, wherein the planarization insulating layer is formed by depositing a liquid insulating material (LPD) that is selectively deposited only on a portion without a photoresist. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950047399A 1995-12-07 1995-12-07 Method of forming multi-layer wiring on the semiconductor device KR0172504B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950047399A KR0172504B1 (en) 1995-12-07 1995-12-07 Method of forming multi-layer wiring on the semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950047399A KR0172504B1 (en) 1995-12-07 1995-12-07 Method of forming multi-layer wiring on the semiconductor device

Publications (2)

Publication Number Publication Date
KR970053517A true KR970053517A (en) 1997-07-31
KR0172504B1 KR0172504B1 (en) 1999-03-30

Family

ID=19438255

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950047399A KR0172504B1 (en) 1995-12-07 1995-12-07 Method of forming multi-layer wiring on the semiconductor device

Country Status (1)

Country Link
KR (1) KR0172504B1 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100758350B1 (en) * 2006-01-19 2007-09-17 김용철 Lighting device with cylinder filters

Also Published As

Publication number Publication date
KR0172504B1 (en) 1999-03-30

Similar Documents

Publication Publication Date Title
KR970067543A (en) Manufacturing Method of Semiconductor Device
KR950034482A (en) Method of forming multi-layer metal wiring of semiconductor device
KR930014785A (en) Contact manufacturing method of multilayer metal wiring structure
KR970053517A (en) Method of forming multilayer wiring structure of semiconductor device
KR970072086A (en) METHOD FOR FORMING METAL WIRING OF SEMICONDUCTOR
KR970077186A (en) Multilayer metallization structure of semiconductor device and method of manufacturing the same
KR19980058383A (en) Metal wiring formation method of semiconductor device
KR960002644A (en) Method of forming interlayer insulating film of semiconductor device
KR970052309A (en) Method for manufacturing metal wiring of semiconductor device
KR100268797B1 (en) How to Form Multilayer Metal Wiring
KR970018413A (en) Method for forming multilayer wiring of semiconductor device
KR980005543A (en) METHOD FOR FORMING METAL WIRING OF SEMICONDUCTOR
KR970053587A (en) A semiconductor device manufacturing method comprising a multilayer metal layer
KR960030374A (en) Planarization method of metal-insulating film
KR970052386A (en) Metal wiring formation method of semiconductor device
KR960002636A (en) Metal interlayer insulating film formation method
KR970003854A (en) How to Form Multilayer Metal Wiring
KR970003522A (en) Metal wiring formation method
KR950021079A (en) Manufacturing Method of Semiconductor Device
KR970023630A (en) Semiconductor device manufacturing method
KR970018177A (en) Manufacturing Method of Semiconductor Device
KR950021414A (en) Connecting process between multilayer wirings of semiconductor device
KR920010877A (en) Metallization Contact Formation Method
KR960005957A (en) How to Form Multilayer Wiring
KR960002681A (en) How to Form Multilayer Metal Wiring

Legal Events

Date Code Title Description
A201 Request for examination
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20090922

Year of fee payment: 12

LAPS Lapse due to unpaid annual fee