KR960030374A - Planarization method of metal-insulating film - Google Patents

Planarization method of metal-insulating film Download PDF

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Publication number
KR960030374A
KR960030374A KR1019950001534A KR19950001534A KR960030374A KR 960030374 A KR960030374 A KR 960030374A KR 1019950001534 A KR1019950001534 A KR 1019950001534A KR 19950001534 A KR19950001534 A KR 19950001534A KR 960030374 A KR960030374 A KR 960030374A
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South Korea
Prior art keywords
insulating film
forming
metal layer
metal
resist
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KR1019950001534A
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Korean (ko)
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KR0182043B1 (en
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황호익
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김광호
삼성전자 주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76819—Smoothing of the dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
    • H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
    • H01L21/31055—Planarisation of the insulating layers involving a dielectric removal step the removal being a chemical etching step, e.g. dry etching
    • H01L21/31056—Planarisation of the insulating layers involving a dielectric removal step the removal being a chemical etching step, e.g. dry etching the removal being a selective chemical etching step, e.g. selective dry etching through a mask

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  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

이 발명은 금속-절연막의 평탄화 방법에 관한 것으로, 반도체 디바이스의 집적도 향상을 위해서는 다층 배선을 형성해야 하는데 이 다층 배선을 형성하는 공정은 반도체 디바이스의 제조공정에서 가장 문제가 발생하기 쉬운 공정이고 제품의 신뢰성 저하를 가져오는 많은 요인을 포함하고 있다.The present invention relates to a planarization method of a metal-insulating film. In order to improve the degree of integration of a semiconductor device, a multilayer wiring must be formed. The process of forming the multilayer wiring is the most prone problem in the manufacturing process of the semiconductor device, and It contains a number of factors that lead to lower reliability.

이러한 다층 배선 공정에서 일어나는 문제점 중에 표면 단차에 의한 것이 있는데 층 배선에서 이 단차가 발생하면 단선이나 층간 접촉 불량이 발생하여 이를 방지하기 위해서 표면의 평탄화 공정이 필요하게 되었다.One of the problems in the multi-layer wiring process is due to the surface level difference. When this step occurs in the layer wiring, the disconnection or the poor contact between layers occurs, and the planarization process of the surface is required to prevent this.

그러나 다층 배선을 형성하기 위해 반도체 기판 위에 배선층을 형성하고 절연막을 형성하는 공정에서 절연막을 평탄화하는 종래의 금속-절연막 평탄화 방법은 금속층에 의하여 발생하는 단차를 완전하게 방지할 수 없었고, 또한 금속층이 조밀하게 형성된 경우에는 절연막 증착시에 홀이 발생하여 절연막이 완전한 절연을 할 수 없다는 문제점이 있었다.However, the conventional metal-insulating film planarization method of planarizing the insulating film in the process of forming the wiring layer on the semiconductor substrate and forming the insulating film to form the multi-layered wiring cannot completely prevent the step caused by the metal layer, and the metal layer is dense. In this case, holes are generated during the deposition of the insulating film, so that the insulating film cannot be completely insulated.

따라서, 이 발명에서는 반도체 기판 위에 절연막을 형성한 후 금속층을 형성하고 다시 제2절연막을 형성하여 종래의 평탄화 방법에서 발생하는 문제점들을 해결 할 수 있도록 하였다.Accordingly, in the present invention, after forming an insulating film on a semiconductor substrate, a metal layer is formed, and then a second insulating film is formed to solve the problems occurring in the conventional planarization method.

Description

금속-절연막의 평탄화 방법Planarization method of metal-insulating film

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제4도 (가), (나), (다), (라), (마)는 이 발명에 따른 평탄화 방법을 나타낸 공정도, 제5도는 이 발명에 따른 평탄화 공정에 의한 반도체 소자의 단면도이다.4 (a), (b), (c), (d) and (e) are process charts showing the planarization method according to the present invention, and FIG. .

Claims (9)

다층 배선 구조를 갖는 반도체 디바이스를 평탄화하는 공정에 있어서, 절연막을 형성한 후 상기한 절연막에 금속층에 형성함을 특징으로 하는 금속-절연막 평탄화 방법.A step of planarizing a semiconductor device having a multi-layered wiring structure, wherein the insulating film is formed, and then a metal layer is formed on the insulating film. 제1항에 있어서, 상기한 절연막에 상기한 금속층을 형성하기 위하여 통로홀을 형성함을 특징으로 하는 금속-절연막 평탄화 방법.The method of claim 1, wherein a passage hole is formed in the insulating film to form the metal layer. 제1항에 있어서, 상기한 절연막과 상기한 금속층을 형성한 후 제2절연막을 형성함을 특징으로 하는 금속-절연막 평탄화 방법.2. The method of claim 1, wherein a second insulating film is formed after forming the insulating film and the metal layer. 제1층간절연막 위에 절연막을 형성하는 공정과 상기한 절연막에 레지스트를 형성하고 상기한 레지스트를 마스크로 하여 상기한 절연막을 에칭하여 통로홀을 형성하는 공정과, 상기한 절연막 위에 또다른 레지스트를 형성하고, 레지스트를 마스크로 하여 상기한 제1층간절연막을 에칭하여 컨택트홀을 형성하는 공정과, 상기한 레지스트를 제거하고 금속막을 형성시키는 공정과, 사진 식각에 의하여 상기한 금속막을 패턴하여 금속층을 형성하는 공정과, 상기한 금속층과 상기한 절연막 위에 제2절연막을 형성시키는 공정을 포함함을 특징으로 하는 금속-절연막 평탄화 방법.Forming an insulating film on the first interlayer insulating film; forming a resist in the insulating film; etching the insulating film using the resist as a mask; forming a passage hole; forming another resist on the insulating film; Forming a contact hole by etching the first interlayer insulating film using a resist as a mask, removing the resist and forming a metal film, and patterning the metal film by photolithography to form a metal layer. And forming a second insulating film over said metal layer and said insulating film. 제4항에 있어서, 상기한 절연막을 형성하는 공정에 있어서 상기한 금속층과 동일한 두께를 갖도록 상기한 절연막을 형성함을 특징으로 하는 금속-절연막 평탄화 방법.5. The method of claim 4, wherein the insulating film is formed to have the same thickness as the metal layer in the step of forming the insulating film. 제4항에 있어서, 상기한 절연막을 에칭하기 위하여 상기한 레지스트를 형성하는 공정에 있어서 상기한 레지스트는 상기한 금속층의 패턴과 반대의 극성을 갖도록 형성함을 특징으로 하는 금속-절연막 평탄화 방법.5. The method of claim 4, wherein the resist is formed to have a polarity opposite to that of the pattern of the metal layer in the step of forming the resist to etch the insulating film. 제4항에 있어서, 상기한 컨택트홀에 상기한 금속층을 형성함을 특징으로 하는 금속-절연막 평탄화 방법.5. The method of claim 4, wherein the metal layer is formed in the contact hole. 제4항에 있어서, 상기한 절연막을 에칭하는데 있어서 습식식각을 이용함을 특징으로 하는 금속-절연막 평탄화 방법.5. The method of claim 4, wherein wet etching is used to etch the insulating film. 제4항 또는 제8항에 있어서, 상기한 절연막을 에칭하여 상기한 절연막의 에칭된 부분이 완만한 경사를 이루도록함을 특징으로 하는 금속-절연막 평탄화 방법.9. The method of claim 4 or 8, wherein the insulating film is etched so that the etched portion of the insulating film has a gentle slope. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950001534A 1995-01-27 1995-01-27 Method for plating metal-insulating layer KR0182043B1 (en)

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KR1019950001534A KR0182043B1 (en) 1995-01-27 1995-01-27 Method for plating metal-insulating layer

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KR960030374A true KR960030374A (en) 1996-08-17
KR0182043B1 KR0182043B1 (en) 1999-04-15

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