KR970053513A

KR970053513A - Method for forming conductive wiring in semiconductor device

Info

Publication number: KR970053513A
Application number: KR1019950046988A
Authority: KR
Inventors: 김현수; 이석규
Original assignee: 김주용; 현대전자산업 주식회사
Priority date: 1995-12-06
Filing date: 1995-12-06
Publication date: 1997-07-31

Abstract

본 발명은 반도체소자의 도전배선 형성방법에 관한 것으로, 반도체기판 상부에 하부도전배선층을 형성하고 상기 하부도전배선층 표면상부를 세척한 다음, DCS, WF₆및 소량의 MS 가스를 반응가스로 하여 텅스텐 실리사이드를 일정온도에서 형성하고 도전배선마스크를 이용한 식각공정을 실시한 다음, 후속열공정을 실시하여 텅스텐이 많은 막이 형성되는 것을 방지함으로써 필링현상을 방지하고 소자의 특성열화를 방지하는 동시에 소자의 동작특성을 향상시켜 반도체소자의 특성, 수율 및 신뢰성을 향상시키고 그에 따른 반도체소자의 고집적화를 가능하게 하는 기술이다.The present invention relates to a method for forming a conductive wiring of a semiconductor device, wherein a lower conductive wiring layer is formed on a semiconductor substrate, and the upper conductive wiring layer is washed on a surface thereof, and then tungsten is used as a reaction gas using DCS, WF ₆ and a small amount of MS gas. The silicide is formed at a constant temperature, followed by an etching process using a conductive wiring mask, followed by a subsequent heat process to prevent the formation of a tungsten-rich film, which prevents peeling and deterioration of device characteristics, while at the same time operating characteristics of the device. In order to improve the characteristics, yield and reliability of the semiconductor device, and to thereby increase the integration of the semiconductor device.

Description

Method for forming conductive wiring in semiconductor device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1A도 내지 제1C도는 본 발명의 실시예에 따른 반도체소자의 도전배선 형성공정을 도시한 단면도.1A to 1C are cross-sectional views showing a process for forming conductive wirings in a semiconductor device according to an embodiment of the present invention.

Claims

Forming a lower conductive wiring layer on a semiconductor substrate by a predetermined thickness, washing the lower conductive wiring layer, forming a tungsten silicide on the lower conductive wiring layer by CVD, and an etching process using a conductive wiring mask. And sequentially etching the tungsten silicide and the lower conductive wiring layer, and performing a subsequent thermal process.

The method of claim 1, wherein the lower conductive wiring layer is formed of a polysilicon film doped in an in-suit process at a temperature of 400 to 700 ℃.

The method of claim 1, wherein the tungsten silicide forming process uses DCS, MS, and WF ₆ gases as reaction gases.

The method of claim 1, wherein the tungsten silicide forming step is performed by using MS gas as 5 to 50 percent of the total flow rate of the DCS gas and the MS gas.

The method of claim 1, wherein the tungsten silicide forming process is performed at a temperature of 500 to 700 ° C. 7.

※ Note: The disclosure is based on the initial application.