KR970053465A - Device Separation Method of Semiconductor Devices - Google Patents

Device Separation Method of Semiconductor Devices Download PDF

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Publication number
KR970053465A
KR970053465A KR1019950066005A KR19950066005A KR970053465A KR 970053465 A KR970053465 A KR 970053465A KR 1019950066005 A KR1019950066005 A KR 1019950066005A KR 19950066005 A KR19950066005 A KR 19950066005A KR 970053465 A KR970053465 A KR 970053465A
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KR
South Korea
Prior art keywords
trench
oxide film
photoresist pattern
semiconductor devices
forming
Prior art date
Application number
KR1019950066005A
Other languages
Korean (ko)
Other versions
KR0172240B1 (en
Inventor
박미라
Original Assignee
김주용
현대전자산업 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김주용, 현대전자산업 주식회사 filed Critical 김주용
Priority to KR1019950066005A priority Critical patent/KR0172240B1/en
Publication of KR970053465A publication Critical patent/KR970053465A/en
Application granted granted Critical
Publication of KR0172240B1 publication Critical patent/KR0172240B1/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)

Abstract

본 발명은 반도체소자의 소자분리 방법에 관한 것으로서, 트랜치의 내측을 순차적으로 형성되는 제1산화막과 감광막패턴으로 메우되, 상기 제1산화막을 트랜치 내측의 일부만 남도록한 후, 상기 감광막패턴을 제거하고 제1산화막을 도포하여 상기 트랜치를 메웠으므로, 트랜치의 내측에 보이드 생성이 억제되어 공정수율 및 소자 동작의 신뢰성을 향상시킬 수 있다.The present invention relates to a device isolation method of a semiconductor device, wherein the inside of a trench is sequentially filled with a first oxide film and a photoresist pattern, and after the first oxide film is partially left inside the trench, the photoresist pattern is removed. Since the trench is filled with the first oxide film, void generation is suppressed inside the trench, thereby improving process yield and reliability of device operation.

Description

반도체 소자의 소자분리 방법Device Separation Method of Semiconductor Devices

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제2a도 내지 제2f도는 본 발명에 따른 반도체소자의 소자분리 공정도.2a to 2f is a device isolation process diagram of a semiconductor device according to the present invention.

Claims (3)

반도체기판에서 소자분리 영역으로 예정되어 있는 부분에 트랜치를 형성하는 공정과, 상기 구조의 전표면에 트랜치를 메우지 않는 정도의 두께로 제1산화막을 형성하는 공정과, 상기 트랜치 내측의 제1산화막 상에 감광막 패턴을 형성하여 상기 트랜치를 메우는 공정과, 상기 제1산화막을 전면 이방성식각하여 상기 트랜치의 내측에만 남도록 하는 공정과, 상기 감광막패턴을 제거하는 공정과, 상기 트랜치를 제2산화막을 메우는 공정을 구비하는 반도체소자의 소자분리 방법.Forming a trench in a portion of the semiconductor substrate that is intended to be an isolation region; forming a first oxide film at a thickness that does not fill the trench on the entire surface of the structure; and a first oxide film inside the trench. Forming a photoresist pattern on the trench to fill the trench, anisotropically etching the first oxide film to leave only the inside of the trench, removing the photoresist pattern, and filling the trench with the second oxide film A device isolation method for a semiconductor device comprising a step. 제1항에 있어서, 상기 제1 및 제2산화막이 TEOS 산화막인 것을 특징으로 하는 반도체소자의 소자분리 방법.2. The method of claim 1, wherein the first and second oxide films are TEOS oxide films. 제1항에 있어서, 상기 트랜치 내측의 제1산화막이 남도록 식각하는 공정시 상기 트랜치의 애스팩트비가 1이 되도록하는 것을 특징으로 하는 반도체소자의 소자분리 방법.The method of claim 1, wherein the aspect ratio of the trench is equal to 1 during the etching of the first oxide layer inside the trench. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950066005A 1995-12-29 1995-12-29 Method of separating element from semiconductor device KR0172240B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950066005A KR0172240B1 (en) 1995-12-29 1995-12-29 Method of separating element from semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950066005A KR0172240B1 (en) 1995-12-29 1995-12-29 Method of separating element from semiconductor device

Publications (2)

Publication Number Publication Date
KR970053465A true KR970053465A (en) 1997-07-31
KR0172240B1 KR0172240B1 (en) 1999-03-30

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ID=19447185

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950066005A KR0172240B1 (en) 1995-12-29 1995-12-29 Method of separating element from semiconductor device

Country Status (1)

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KR (1) KR0172240B1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100620706B1 (en) * 2004-12-31 2006-09-13 동부일렉트로닉스 주식회사 Method for Forming the Isolation Layer of Semiconductor Device

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100401527B1 (en) * 1996-04-24 2003-12-24 주식회사 하이닉스반도체 Isolation method of semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100620706B1 (en) * 2004-12-31 2006-09-13 동부일렉트로닉스 주식회사 Method for Forming the Isolation Layer of Semiconductor Device

Also Published As

Publication number Publication date
KR0172240B1 (en) 1999-03-30

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