KR970053402A - Device Separation Method of Semiconductor Device - Google Patents

Device Separation Method of Semiconductor Device Download PDF

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Publication number
KR970053402A
KR970053402A KR1019950052725A KR19950052725A KR970053402A KR 970053402 A KR970053402 A KR 970053402A KR 1019950052725 A KR1019950052725 A KR 1019950052725A KR 19950052725 A KR19950052725 A KR 19950052725A KR 970053402 A KR970053402 A KR 970053402A
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KR
South Korea
Prior art keywords
oxide film
semiconductor device
layer
film
depositing
Prior art date
Application number
KR1019950052725A
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Korean (ko)
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KR0170356B1 (en
Inventor
황병근
최지현
구주선
이해정
Original Assignee
김광호
삼성전자주식회사
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Priority to KR1019950052725A priority Critical patent/KR0170356B1/en
Publication of KR970053402A publication Critical patent/KR970053402A/en
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Publication of KR0170356B1 publication Critical patent/KR0170356B1/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76227—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials the dielectric materials being obtained by full chemical transformation of non-dielectric materials, such as polycristalline silicon, metals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H01L21/02134—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material comprising hydrogen silsesquioxane, e.g. HSQ

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)

Abstract

본 발명은 화학 기계적 연마(Chemical mechanical polishing; CMP)공정시 나타나는 소자간의 단차를 개선하는 반도체 장치의 소자 분리 방법에 관한 것으로서, 트랜치 형성 후 절연체를 매몰시켜 반도체 장치의 소자 분리 방법은 산화막으로 변질되는 층을 증착하는 단계;, 상기 증착된 층을 코팅하는 단계; 및 상기 코팅된 층을 습식 어닐하는 단계를 포함한다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a device isolation method of a semiconductor device that improves a step difference between devices that appear during a chemical mechanical polishing (CMP) process. The method of device separation of a semiconductor device is performed by burying an insulator after trench formation. Depositing a layer, coating the deposited layer; And wet annealing the coated layer.

따라서, 상술한 바와 같이 본 발명에 따른 반도체 장치의 소자 분리 방법은 트랜치 내부에 아몰퍼스 실리콘(A-SI)을 증착한 후, 플루어블 옥사이드(Flowable Oxide)를 매몰하고(FILL), 습식 어닐함으로써, 전체적으로 딱딱하게 트랜치를 매몰하고, 이후 공정인 화학 기계적 연마(Chemical mechanical polishing; CMP)공정시 소자간의 단차를 개선하는 효과를 갖는다.Therefore, as described above, in the device isolation method of the semiconductor device according to the present invention, after depositing amorphous silicon (A-SI) in the trench, the oxide is buried (FILL) and wet annealed. In addition, the trench is hardly buried as a whole, and the step of chemical mechanical polishing (CMP) is improved.

Description

반도체 장치의 소자 분리 방법Device Separation Method of Semiconductor Device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제7(a)도 내지 제7(d)도는 본 발명에 따른 트랜치 형성 후의 수직단면도를 보이는 도면이다.7 (a) to 7 (d) show a vertical cross-sectional view after trench formation according to the present invention.

Claims (5)

트랜치 형성 후 절연체를 매몰시켜 반도체 장치의 소자 분리 방법에 있어서, 산화막으로 변질되는 층을 증착하는 단계; 상기 증착된 층을 플루어블 산화막으로 코팅하는 단계; 및 상기 코팅된 산화막을 습식 어닐하는 단계를 포함하는 것을 특징으로 하는 반도체 장치의 소자 분리 방법.A method of isolating a device of a semiconductor device by burying an insulator after trench formation, the method comprising: depositing a layer deteriorated with an oxide film; Coating the deposited layer with a flexible oxide film; And wet annealing the coated oxide film. 제1항에 있어서, 상기 증착단계는 아몰퍼스 실리콘이나 폴리 실리콘을 사용하는 것을 특징으로 하는 반도체 장치의 소자 분리 방법.2. The method of claim 1, wherein the depositing step comprises amorphous silicon or polysilicon. 제1항에 있어서, 상기 증착막을 형성하기 전에 산화막이나 질화막을 형성하는 것을 특징으로 하는 반도체 장치의 소자 분리 방법.The device isolation method according to claim 1, wherein an oxide film or a nitride film is formed before the deposition film is formed. 제1항에 있어서, 상기 습식 어닐단계는 500 ℃이상의 습식분위기에서 상기 산화막으로 변질되는 층을 산화시키고 플루어블 산화막을 경화시키는 것을 특징으로 하는 반도체 장치의 소자 분리 방법.2. The method of claim 1, wherein the wet annealing step oxidizes the layer deteriorated with the oxide film in a wet atmosphere of 500 ° C. or more, and hardens the flexible oxide film. 제1항에 있어서, 상기 플루어블 산화막은 하이드로건 실세큐 옥시렌(hydrogen silsequeoxane)막을 형성하는 것을 특징으로 하는 반도체 장치의 소자 분리 방법.The method of claim 1, wherein the flexible oxide film forms a hydrogen silsequeoxane film. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950052725A 1995-12-20 1995-12-20 Element separating method of semiconductor device KR0170356B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950052725A KR0170356B1 (en) 1995-12-20 1995-12-20 Element separating method of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950052725A KR0170356B1 (en) 1995-12-20 1995-12-20 Element separating method of semiconductor device

Publications (2)

Publication Number Publication Date
KR970053402A true KR970053402A (en) 1997-07-31
KR0170356B1 KR0170356B1 (en) 1999-03-30

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KR1019950052725A KR0170356B1 (en) 1995-12-20 1995-12-20 Element separating method of semiconductor device

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KR0170356B1 (en) 1999-03-30

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