KR970052457A - Method for forming micro contact hole in semiconductor device - Google Patents

Method for forming micro contact hole in semiconductor device Download PDF

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Publication number
KR970052457A
KR970052457A KR1019950066046A KR19950066046A KR970052457A KR 970052457 A KR970052457 A KR 970052457A KR 1019950066046 A KR1019950066046 A KR 1019950066046A KR 19950066046 A KR19950066046 A KR 19950066046A KR 970052457 A KR970052457 A KR 970052457A
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KR
South Korea
Prior art keywords
contact
forming
mask
contact hole
contact mask
Prior art date
Application number
KR1019950066046A
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Korean (ko)
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KR0172547B1 (en
Inventor
이병렬
김정
Original Assignee
김주용
현대전자산업 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
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Application filed by 김주용, 현대전자산업 주식회사 filed Critical 김주용
Priority to KR1019950066046A priority Critical patent/KR0172547B1/en
Publication of KR970052457A publication Critical patent/KR970052457A/en
Application granted granted Critical
Publication of KR0172547B1 publication Critical patent/KR0172547B1/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76804—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics by forming tapered via holes
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
    • G03F1/36—Masks having proximity correction features; Preparation thereof, e.g. optical proximity correction [OPC] design processes

Abstract

본 발명은 반도체 소자의 미세 콘택홀 형성방법에 관한 것으로, 콘택 마스크를 종래의 주콘택 마스크 외측둘레로 링형패턴을 첨가시킨 형태로 함으로써 콘택 형성을 위한 하부 감광막 패턴 형성시 빛의 간섭에 의해 그 측벽이 경사지도록 하여 콘택홀 식각시 공정마진을 증가시킴과 아울러, 미세콘택홀 형성을 용이하게 할 수 있다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a fine contact hole in a semiconductor device. The contact mask is formed by adding a ring-shaped pattern around the outer side of a conventional main contact mask. By making the inclination increase, the process margin may be increased during the etching of the contact hole, and the formation of the fine contact hole may be facilitated.

Description

반도체 소자의 미세콘택홀 형성방법Method for forming micro contact hole in semiconductor device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제2A도는 본 발명에 따른 콘택 마스크의 레이아웃도.2A is a layout diagram of a contact mask according to the present invention.

제2B도는 제2A도의 B-B선에 따른 단면도.FIG. 2B is a cross-sectional view taken along the line B-B in FIG. 2A.

제2C도는 식각에 의해 콘택홀을 형성한 상태의 단면도.2C is a cross-sectional view of a state in which a contact hole is formed by etching.

Claims (6)

반도체 기판상의 예정된 위치에 소자 분리를 위한 필드 산화막을 형성하는 단계와, 반도체 기판상에 활성영역을 위한 불순물을 주입하는 단계와, 전체구조 상부에 층간 절연막을 형성하는 단계와, 전체구조 상부에 소정두께의 감광막을 형성하는 단계와, 콘택 마스크를 사용하여 하부의 감광막을 노광 및 현상하여 감광막 패턴을 형성하는 단계와, 상기 감광막 패턴을 이용하여 하부절연막을 식각하여 콘택홀을 형성하는 단계와, 감광막을 제거하는 단계를 구비하는 콘택홀 형성방법에 있어서, 상기 감광막 패턴 형성을 위한 콘택 마스크로 콘택 마스크 외측둘레로 링형 패턴을 첨가시킨 형태의 마스크를 사용하여 마스크 작업시 빛의 간섭이 생겨 감광막 패턴의 측벽면이 일정각도 경사지게 형성되도록한 것을 특징으로 하는 반도체 소자의 미세콘택홀 형성방법.Forming a field oxide film for device isolation at a predetermined position on the semiconductor substrate, implanting an impurity for an active region on the semiconductor substrate, forming an interlayer insulating film over the entire structure, and forming a predetermined upper portion over the entire structure Forming a photoresist layer having a thickness, exposing and developing a lower photoresist layer using a contact mask to form a photoresist pattern, and etching a lower insulating layer using the photoresist pattern to form contact holes; In the method for forming a contact hole comprising the step of removing the photoresist pattern, using a mask of the form in which a ring-shaped pattern is added around the outer side of the contact mask as a contact mask for forming the photoresist pattern, the light interference occurs during the mask operation The micro contact hole of the semiconductor device, characterized in that the side wall surface is formed to be inclined at a predetermined angle Formation method. 제1항에 있어서, 상기 콘택 마스크는 메모리 셀의 비트라인 콘택 및 스토리지노드 콘택을 각각 형성할 시 적용되는 것을 특징으로 하는 반도체 소자의 미세콘택홀 형성방법.The method of claim 1, wherein the contact mask is applied to each of forming a bit line contact and a storage node contact of a memory cell. 제1항에 있어서, 상기 콘택 마스크는 메모리셀의 비트라인 콘택 및 스토리지노드 콘택을 동시에 형성할 시 적용되는 것을 특징으로 하는 반도체 소자의 미세 콘택홀 형성방법.The method of claim 1, wherein the contact mask is applied when simultaneously forming a bit line contact and a storage node contact of a memory cell. 제1항에 있어서, 상기 콘택 마스크는 반도체 소자의 금속배선을 위한 콘택홀 형성시 적용도는 것을 특징으로 하는 반도체 소자의 미세콘택홀 형성방법.The method of claim 1, wherein the contact mask is applied when forming a contact hole for metal wiring of the semiconductor device. 제1항에 있어서, 상기 콘택 마스크의 외측둘레에 구비되는 링형 패턴의 수는 2개~4개인 것을 특징으로 하는 반도체 소자의 미세콘택홀 형성방법.The method of claim 1, wherein the number of ring-shaped patterns provided on the outer circumference of the contact mask is two to four. 제1항에 있어서, 상기 주 콘택 마스크와 링형패턴 사이의 간격은 적정간격으로 조절할 수 있도록 구비된 것을 특징으로 하는 반도체 소자의 미세콘택홀 형성방법.The method of claim 1, wherein an interval between the main contact mask and the ring-shaped pattern is adjusted to be appropriately spaced apart. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950066046A 1995-12-29 1995-12-29 Method of forming contact hole of semiconductor device KR0172547B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950066046A KR0172547B1 (en) 1995-12-29 1995-12-29 Method of forming contact hole of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950066046A KR0172547B1 (en) 1995-12-29 1995-12-29 Method of forming contact hole of semiconductor device

Publications (2)

Publication Number Publication Date
KR970052457A true KR970052457A (en) 1997-07-29
KR0172547B1 KR0172547B1 (en) 1999-03-30

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KR1019950066046A KR0172547B1 (en) 1995-12-29 1995-12-29 Method of forming contact hole of semiconductor device

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KR (1) KR0172547B1 (en)

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Publication number Publication date
KR0172547B1 (en) 1999-03-30

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