KR970023726A - Microcontact Formation Method of Semiconductor Device - Google Patents

Microcontact Formation Method of Semiconductor Device Download PDF

Info

Publication number
KR970023726A
KR970023726A KR1019950036614A KR19950036614A KR970023726A KR 970023726 A KR970023726 A KR 970023726A KR 1019950036614 A KR1019950036614 A KR 1019950036614A KR 19950036614 A KR19950036614 A KR 19950036614A KR 970023726 A KR970023726 A KR 970023726A
Authority
KR
South Korea
Prior art keywords
forming
insulating film
entire surface
bit line
contact
Prior art date
Application number
KR1019950036614A
Other languages
Korean (ko)
Other versions
KR100195837B1 (en
Inventor
박철수
김진웅
정명준
Original Assignee
김주용
현대전자산업주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김주용, 현대전자산업주식회사 filed Critical 김주용
Priority to KR1019950036614A priority Critical patent/KR100195837B1/en
Publication of KR970023726A publication Critical patent/KR970023726A/en
Application granted granted Critical
Publication of KR100195837B1 publication Critical patent/KR100195837B1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

본 발명은 반도체소자의 미세콘택 형성방법에 관한 것으로, 반도체 기판 상부에 소자분리 절연막을 형성하고 워드라인을 형성하되, 상기 소자분리절연막이 형성된 비활성영역의 워드라인간의 간격은 “α”만큼 좁게 형성하고 활성영역은“β”만큼 넓게 형성하는 동시에 상기 반도체기판의 예정된 부분을 노출시키는 캐패시터 콘택홀과 비트라인 콘댁홀을 형성한 다음, 전체표면상부에 스페이서용 절연막을 일정두께 형성하되, 상기 비활성영역의 워드 라인간의 간격을 매립하고 이를 전면식각하여 상기 활성영역의 워드라인 측벽에 절연막 스페이서를 형성한 다음, 상기 콘택홀의 측벽 및 저부에 도전층을 일정두께 형성하고 비트라인 형성공정 및 캐패시터 형성공정으로 상기 콘택홀 상부의 도전층에 접속되는 캐패시터와 비트라인을 형성함으로써 주변의 구조물과 쇼트없이 콘택을 형성하여 최소그래피의 한계를 극복함으로써 반도체소자의 특성, 수율 및 신뢰성을 향상시키고 그에 따른 반도체소자의 고집적화를 가능하게 하는 기술이다.The present invention relates to a method for forming a micro contact of a semiconductor device, wherein a device isolation insulating film is formed on the semiconductor substrate and a word line is formed, but the spacing between word lines of the inactive region where the device isolation insulating film is formed is as narrow as “α”. And forming a capacitor contact hole and a bit line contact hole exposing a predetermined portion of the semiconductor substrate as wide as “β”, and then forming an insulating layer for spacers over the entire surface, wherein the insulating layer is formed to have a predetermined thickness. Filling the gaps between the word lines and etching the entire surface to form insulating film spacers on the sidewalls of the word lines of the active region, and then forming a conductive layer on the sidewalls and bottoms of the contact holes, and forming a bit line and a capacitor forming process. By forming a bit line and a capacitor connected to the conductive layer on the contact hole Is by overcoming the limits of our minimum to form a contact without the surrounding structure and the short-improving the characteristics of the semiconductor device, the yield and reliability and technology that enables high integration of the semiconductor device thereof.

Description

반도체 소자의 미세콘택 형성방법Microcontact Formation Method of Semiconductor Device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제 1 도는 본 발명에 따른 반도체소자 레이아웃도.1 is a layout diagram of a semiconductor device in accordance with the present invention.

Claims (2)

반도체기판 상부에 소자분리절연막을 형성하는 공정과, 워드라인마스크를 이용하여 상기 반도체기판 상부에 게이트산화막, 게이트전극 및 층간절연막으로 구성된 워드라인을 형성하되, 소자분리절연막이 형성되어 있는 비활성영역은 워드라인간의 거리를 “α”만큼 넓게 형성하고 활성영역의 콘택부분은 리드라인간의 거리를 “β”만큼 넓게 형성하여 상기 반도체기판의 예정된 부분을 노출시키는 개패시터 콘택홀과 비트라인 콘택홀을 형성하되, β〉α〉0인 공정과, 전체표면상부에 스페이서용 절연막을 일정두께 형성하되, 상기 소자 분리절연막 상부는 워드라인 간의 거리가 좁아 평탄화되는 공정과, 상기 스페이서용 절연막을 전면식각하여 상기 활성영역의 워드라인 측벽에 절연막 스페이서를 형성하는 동시에 상기 비활성 영역은 워드라인을 노출시키는 공정과, 전체표면상부에 일정두께 도전층을 형성하는 공정과, 상기 콘택홀 전체에만 중첩되는 감광막패턴을 형성하는 공정과, 상기 감광막패턴을 마스크로하여 상기 도전층을 식각하는 공정과, 상기 감광막패턴을 제거하는 공정과, 전체표면상부에 제1평탄화층을 형성하는 공정과, 비트라인 콘택마스크를 이용한 식각공정으로 상기 비트라인 콘택홀 상부의 도전층에 접속되는 비트라인을 형성하는 공정과, 전체표면상부에 제2평탄화층을 형성하는 공정과, 캐패시터 콘택마스크를 이용한 식각공정으로 상기 캐패시터 콘택홀 상부의 도전층에 접속되는 캐패시터를 형성하는 공정을 포함하는 반도체 소자의 미세콘택 형성방법.Forming a device isolation insulating film on the semiconductor substrate, and forming a word line including a gate oxide film, a gate electrode, and an interlayer insulating film on the semiconductor substrate by using a word line mask. Form the distance between word lines as wide as “α” and the contact portion in the active area as wide as “β” to form capacitor contact holes and bit line contact holes exposing predetermined portions of the semiconductor substrate. Wherein, the process of β> α> 0, and forming a spacer insulating film on the entire surface, the upper surface of the device isolation insulating film is planarized by narrowing the distance between the word lines, and by etching the entire surface of the spacer insulating film An insulating layer spacer is formed on the sidewalls of the word line of the active region, and the inactive region forms a word line. Exposing, forming a conductive layer on the entire surface, and forming a photoresist pattern overlapping only the entire contact hole; etching the conductive layer using the photoresist pattern as a mask; Removing the photoresist pattern, forming a first flattening layer over the entire surface, and forming a bit line connected to the conductive layer on the bit line contact hole by an etching process using a bit line contact mask. And forming a second planarization layer on the entire surface, and forming a capacitor connected to the conductive layer on the capacitor contact hole by an etching process using a capacitor contact mask. . 제 1 항에 있어서, 상기 스페이서용 절연막의 두께는 α/2×스페이서용 절연막의 단차피복비 만큼인 것을 특징으로하는 반도체소자의 미세콘택 형성방법.2. The method of forming a micro contact of a semiconductor device according to claim 1, wherein the thickness of said insulating film for spacers is as high as the step coverage ratio of said insulating film for spacers. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950036614A 1995-10-23 1995-10-23 Micro contact forming method of semiconductor device KR100195837B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950036614A KR100195837B1 (en) 1995-10-23 1995-10-23 Micro contact forming method of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950036614A KR100195837B1 (en) 1995-10-23 1995-10-23 Micro contact forming method of semiconductor device

Publications (2)

Publication Number Publication Date
KR970023726A true KR970023726A (en) 1997-05-30
KR100195837B1 KR100195837B1 (en) 1999-06-15

Family

ID=19430945

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950036614A KR100195837B1 (en) 1995-10-23 1995-10-23 Micro contact forming method of semiconductor device

Country Status (1)

Country Link
KR (1) KR100195837B1 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100431323B1 (en) * 1997-11-01 2004-06-16 주식회사 하이닉스반도체 Exposure mask

Also Published As

Publication number Publication date
KR100195837B1 (en) 1999-06-15

Similar Documents

Publication Publication Date Title
KR980006303A (en) Capacitor Manufacturing Method of Semiconductor Device
KR970023726A (en) Microcontact Formation Method of Semiconductor Device
KR960019522A (en) Plug Formation Method for Semiconductor Devices
KR100271786B1 (en) Method for forming capacitor electrode of semiconductor device
KR970052384A (en) Method for forming contact hole in semiconductor device
KR0155787B1 (en) Formation method of contact hole in semiconductor device
KR960002842A (en) Method for manufacturing charge storage electrode of semiconductor device
KR940016479A (en) Contact manufacturing method of semiconductor device
KR970054008A (en) Capacitor Manufacturing Method of Semiconductor Device
KR930014972A (en) Contact Manufacturing Method for Highly Integrated Devices
KR970024210A (en) DRAM manufacturing method of semiconductor device
KR970053571A (en) Semiconductor device and manufacturing method thereof
KR960002825A (en) Capacitor Manufacturing Method of Semiconductor Device
KR960039356A (en) Method for manufacturing charge storage electrode of semiconductor device
KR970054036A (en) Capacitor Manufacturing Method of Semiconductor Device
KR960005957A (en) How to Form Multilayer Wiring
KR970024226A (en) Storage electrode formation method of semiconductor memory device
KR970030326A (en) Contact hole formation method of semiconductor device
KR970012990A (en) Capacitor Manufacturing Method Using Self Alignment
KR970013348A (en) Capacitor Manufacturing Method of Semiconductor Device
KR950030338A (en) Capacitor Manufacturing Method of Semiconductor Device
KR970051931A (en) Semiconductor memory device and manufacturing method thereof, mask used therein
KR970054004A (en) Bit line formation method of semiconductor device
KR970054081A (en) Memory Capacitors and Methods of Manufacturing the Same
KR940016933A (en) Method of forming a capacitor of a semiconductor device

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20110126

Year of fee payment: 13

LAPS Lapse due to unpaid annual fee