KR960002842A - Method for manufacturing charge storage electrode of semiconductor device - Google Patents

Method for manufacturing charge storage electrode of semiconductor device Download PDF

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Publication number
KR960002842A
KR960002842A KR1019940014577A KR19940014577A KR960002842A KR 960002842 A KR960002842 A KR 960002842A KR 1019940014577 A KR1019940014577 A KR 1019940014577A KR 19940014577 A KR19940014577 A KR 19940014577A KR 960002842 A KR960002842 A KR 960002842A
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South Korea
Prior art keywords
layer
pattern
insulating
forming
insulating film
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KR1019940014577A
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Korean (ko)
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금동렬
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김주용
현대전자산업 주식회사
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Priority to KR1019940014577A priority Critical patent/KR960002842A/en
Publication of KR960002842A publication Critical patent/KR960002842A/en

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

본 발명은 반도체소자의 전하보존전극 제조방법에 관한것으로서, 소정구조의 반도체기판상에 전하보존전극콘택홀을 구비하는 평탕화츠을 형성하고, 상기 전하보존전극 콘택홀을 메우는 제1폴리실리콘층과 제1절연막을 순차적으로 형성한 후, 상기 제1절연막의 일측을 노출시키는 감광막패턴을 마스크로하여 노출되어 있는 제1절연막에만 선택적으로 저압증착방법으로 제2절연막을 형성하고ㅡ 상기 제1절연막과 제2절연막의 표면에 제2폴리실리콘층을 도포한 후, 전하보존전극 마스크와 캐패시터 마스크로 이중 노광하여 형성된 감광막패턴을 마스크로 상기 제1 및 제2폴리실리콘층을 패턴잉하여 전하보존전극 콘택홀을 메운 제1폴리실리콘층 패턴과 상측 일부가 제거되어 제2절연막의 상측을 노출시키는 제2폴리실리콘층 패턴을 형성하고, 상기 구조의 측벽에 도전 스페이서를 형성하여 사기 제1 및 제2폴리실리콘층 패턴을 연결하여 전하보존전극을 구성하였으므로, 공정이 간단하고 전하보존전극의 표면적이 증가되어 소자동작의 신뢰성과 공정수율을 향상시킬 수 있다.The present invention relates to a method for manufacturing a charge preserving electrode of a semiconductor device, comprising: forming a flattening trough having a charge preserving electrode contact hole on a semiconductor substrate having a predetermined structure, and filling the charge preserving electrode contact hole with a first polysilicon layer; After the first insulating film was formed sequentially, a second insulating film was formed by a low pressure deposition method selectively on only the first insulating film exposed by using a photosensitive film pattern exposing one side of the first insulating film as a mask. After applying the second polysilicon layer on the surface of the second insulating layer, the first and second polysilicon layers are patterned using a photosensitive film pattern formed by double exposure with a charge storage electrode mask and a capacitor mask to form a charge storage electrode contact. The first polysilicon layer pattern filling the hole and a portion of the upper side are removed to form a second polysilicon layer pattern exposing the upper side of the second insulating layer. A conductive spacer was formed on the sidewalls of the first and second polysilicon layer patterns to form a charge storage electrode, thereby simplifying the process and increasing the surface area of the charge storage electrode, thereby improving reliability and process yield. Can be.

Description

반도체소자의 전하보존전극 제조방법Method for manufacturing charge storage electrode of semiconductor device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제1A도 내지 제1G도는 본 발명에 따른 반도체소자의 전하보존전극 제조공정도.1A to 1G are manufacturing process diagrams of a charge storage electrode of a semiconductor device according to the present invention.

Claims (6)

소자분리 절연막과 일련의 워드라인 및 소오스전극이 형성되어 있는 반도체기판상에 제1절연박을 형성하는 공정과, 상기 소오스전극상의 제1절연막을 제거하여 소오스전극을 노출시키는 전하보존전극 콘택홀을 형성하는 공정과, 상기 전하보존전극 콘택홀을 통하여 상기 소오스전극과 접촉되는 제1도전층을 형성하는공정과, 상기 제1도전층상에 제2절연막을 형성하는 공정과, 상기 제2절연막의 일측을 노출시키는 제1감광막패턴을 형성하는 공정과, 상기 제1감광막패턴에의해 노출되어 있는 제2절연막에서 제3절연막을 형성하는 공정과, 상기 제1감광막 패턴을 제거하고상기 구조의 전표면에 제2도전층을 도포하는 공정과, 상기 구조의 전표면에 제4절연막을 도포하는 공정과, 상기 제4절연막상에 상기 제3절연막상의 상측 일부와 전하보존전극을 예정되지 않은 부분을 노출시키는 제2감광막패턴을 형성하는 공정과, 상기 제2감광막패턴에 의해 노출되어 있는 제4절연막에서 제1도전층까지 순차적으로 제거하고, 상기 제3절연막상의 제2도 전층을 제거하여 전하보존전극 콘택홀을 메우는 제1도전층 패턴과 상측 일부의 제3절연막을 노출시키는 제2도전층 패턴을 형성하는 공정과, 상기 제2감광막 패턴을 제거하고 상기 제1도전층 패턴에서 제4절연막 패턴까지의 측벽에 도전 스페이서를 형성하여 상기 제1및 제2도전층 패턴을 연결하는 공정을 구비하는 반도체소자의 전하보존전극 제조방법.Forming a first insulating foil on a semiconductor substrate having a device isolation insulating film, a series of word lines and a source electrode; and a charge storage electrode contact hole exposing the source electrode by removing the first insulating layer on the source electrode. Forming a layer, forming a first conductive layer in contact with the source electrode through the charge storage electrode contact hole, forming a second insulating layer on the first conductive layer, and one side of the second insulating layer Forming a first photoresist pattern that exposes the first photoresist layer; forming a third insulation layer from the second insulation layer exposed by the first photoresist layer pattern; and removing the first photoresist layer pattern to the entire surface of the structure. Applying a second conductive layer; applying a fourth insulating film to the entire surface of the structure; Forming a second photoresist pattern that exposes the portion of the second photoresist layer, and sequentially removing the fourth insulating film exposed by the second photoresist film pattern from the fourth insulating film to the first conductive layer, and removing the second conductive layer on the third insulating film. Forming a first conductive layer pattern filling the charge storage electrode contact hole and a second conductive layer pattern exposing a portion of the third insulating layer on the upper side thereof, and removing the second photoresist layer pattern and removing the second conductive layer pattern from the first conductive layer pattern. And forming a conductive spacer on sidewalls up to a fourth insulating film pattern to connect the first and second conductive layer patterns. 제1항에 있어서, 상기 제1 및 제2도전층과 도전 스페이서를 폴리실리콘층으로 형성하는 것을 특징으로 하는 반도체소자의 전하보존전극 제조방법.The method of claim 1, wherein the first and second conductive layers and the conductive spacer are formed of a polysilicon layer. 제1항에 있어서, 상기 제1절연막의 상측과 제1도전층의사이에 식각장벽층을 개재하는 것을 특징으로 하는 반도체소자의 전하보존전극 제조방법.The method of claim 1, wherein an etching barrier layer is interposed between the upper side of the first insulating layer and the first conductive layer. 제3항에 있어서, 상기 제1절연막과 식가장벽층을 각각 BPSG와 TEOS로 형성하는 것을 특징으로 하는 반도체소자의 전하보존전극 제조방법.The method of claim 3, wherein the first insulating layer and the food barrier layer are formed of BPSG and TEOS, respectively. 제1항에 있어서, 상기 제3절연막이 저압증착방법으로 형성하는 것을 특징으로 하는 반도체소자의 전하보존전극 제조방법.The method of claim 1, wherein the third insulating layer is formed by a low pressure deposition method. 제1항에 있어서, 상기 제4절연막을 유동성이 우수한 O3로 형성하는 것을 특징으로 하는 반도체소자의 전하보존전극 제조방법.The method of claim 1, wherein the fourth insulating layer is formed of O 3 having excellent fluidity. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019940014577A 1994-06-24 1994-06-24 Method for manufacturing charge storage electrode of semiconductor device KR960002842A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019940014577A KR960002842A (en) 1994-06-24 1994-06-24 Method for manufacturing charge storage electrode of semiconductor device

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Application Number Priority Date Filing Date Title
KR1019940014577A KR960002842A (en) 1994-06-24 1994-06-24 Method for manufacturing charge storage electrode of semiconductor device

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KR960002842A true KR960002842A (en) 1996-01-26

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KR1019940014577A KR960002842A (en) 1994-06-24 1994-06-24 Method for manufacturing charge storage electrode of semiconductor device

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