KR970052455A - Barrier metal formation method of semiconductor device - Google Patents

Barrier metal formation method of semiconductor device Download PDF

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Publication number
KR970052455A
KR970052455A KR1019950066011A KR19950066011A KR970052455A KR 970052455 A KR970052455 A KR 970052455A KR 1019950066011 A KR1019950066011 A KR 1019950066011A KR 19950066011 A KR19950066011 A KR 19950066011A KR 970052455 A KR970052455 A KR 970052455A
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KR
South Korea
Prior art keywords
barrier metal
rtp
semiconductor device
temperature
annealing
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Application number
KR1019950066011A
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Korean (ko)
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KR0171948B1 (en
Inventor
권성수
Original Assignee
김주용
현대전자산업 주식회사
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Application filed by 김주용, 현대전자산업 주식회사 filed Critical 김주용
Priority to KR1019950066011A priority Critical patent/KR0171948B1/en
Publication of KR970052455A publication Critical patent/KR970052455A/en
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Publication of KR0171948B1 publication Critical patent/KR0171948B1/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
    • H01L21/76861—Post-treatment or after-treatment not introducing additional chemical elements into the layer
    • H01L21/76864—Thermal treatment

Abstract

본 발명은 반도체소자의 장벽금속 형성방법에 관한 것으로, 튜브에 의한 어닐링방법의 장점과 RTP에 의한 어닐링방법의 장점을 모두 이용하는 2단계 RTP 어닐링방법의 반도체소자의 장벽금속 형성방법에 있어서, 튜브에 의한 어닐링공정의 단점과 RTP에 의한 어닐링공정의 단점을 보완하기 위해 2단계 RTP 어닐링 방법을 사용하되, 첫 번째 단계는 TiN/Ti 구조의 장벽금속 구조에서 장벽과 접합 간의 접촉 저항을 줄이기 위한 단계로 N2분위기만을 사용하며, 어닐링 온도는 600 내지 800℃, 시간은 10 내지 50초로 하여 실시하며, 두 번째 단계는 연속적으로 실시하되, 장벽금속에 O2를 스터핑시키는 단계로 온도는 500 내지 700℃, 시간은 30 내지 120초, 분위기는 N2: O2의 비(N2/O2)가 10 내지 20인 범위에서 실시하여 장벽 특성을 향상시켜 반도체소자의 특성 및 신뢰성을 향상시키고, 그에 따른 반도체소자의 고집적화를 가능하게 하는 기술이다.The present invention relates to a method of forming a barrier metal of a semiconductor device, the method of forming a barrier metal of a semiconductor device of a two-stage RTP annealing method using both the advantages of the annealing method by the tube and the annealing method by the RTP, In order to compensate for the shortcomings of the annealing process by RTP and the annealing process by RTP, a two-step RTP annealing method is used. Only using N 2 atmosphere, the annealing temperature is carried out to 600 to 800 ℃, time to 10 to 50 seconds, the second step is carried out continuously, the step of stuffing O 2 to the barrier metal temperature is 500 to 700 ℃ , The time is 30 to 120 seconds, the atmosphere is carried out in the range of N 2 : O 2 ratio (N 2 / O 2 ) of 10 to 20 to improve the barrier properties to improve the characteristics and characteristics of the semiconductor device It is a technology that improves the reliability and thereby enables high integration of semiconductor devices.

Description

반도체소자의 장벽금속 형성방법Barrier metal formation method of semiconductor device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제1도는 본 발명의 실시예에 따른 반도체소자의 장벽금속 형성방법을 도시한 관계도로서, 2단계 RTP 어닐링공정을 시간에 따른 온도에 따라 도시한 그래프도이다.FIG. 1 is a relation diagram illustrating a method of forming a barrier metal of a semiconductor device according to an exemplary embodiment of the present invention, and is a graph illustrating a two-step RTP annealing process with temperature over time.

Claims (2)

공지의 기술로 장벽금속을 형성하고, 상기 장벽금속의 특성을 향상시키기 위하여, 튜브에 의한 어닐링방법의 장점과 RTP에 의한 어닐링방법의 장점을 모두 이용하는 2단계 RTP 어닐링방법의 반도체소자의 장벽금속 형성방법에 있어서, 상온에서 RTP 챔버를 안정화 시키기 위해 N2를 10 내지 100초 동안 흘려주는 단계와, 상기 N2분위기 하에서 600 내지 800℃까지 가열비를 30 내지 100℃/sec로 하여 가열하는 단계와, 상기 N2분위기 600 내지 800℃ 온도에서 10 내지 50초 정도 가열하여 TiSi2를 형성하는 단계와, 상기 RTP 챔버의 온도를 400 내지 500℃ 정도로 하강시켜 안정화시키는 단계와, 상기 챔버에 N2와 O2혼합 가스를 10 내지 30초 정도 흘려 상기 챔버를 안정화시키는 단계와, 상기 TiN 장벽금속 내에 O2스터핑이 용이하게 되는 온도까지 상승시켜 스터핑시키는 단계와, 상기 RTP 챔버 내의 웨이퍼 온도를 상온으로 떨어뜨리는 공정을 포함하는 반도체소자의 장벽금속 형성방법.In order to form a barrier metal by using a known technique and to improve the properties of the barrier metal, barrier metal formation of a semiconductor device of a two-stage RTP annealing method using both the advantages of an annealing method by a tube and an annealing method by an RTP. In the method, the step of flowing N 2 for 10 to 100 seconds to stabilize the RTP chamber at room temperature, and heating at a heating ratio of 30 to 100 ℃ / sec to 600 to 800 ℃ under the N 2 atmosphere and , and with the method comprising the N 2 atmosphere is heated at 600 to 800 ℃ temperature of 10 to 50 seconds to form a TiSi 2, stabilizing moved down about 400 to about 500 ℃ the temperature of the RTP chamber, N 2 to the chamber O 2 gas mixture was raised to the steps and, the temperature at which the O 2 stuffing is easy in the TiN barrier metal to flow stabilizing the chamber for 10 to 30 seconds to the stuffing ; And how the barrier metal formed of a semiconductor device, which comprises the steps dropping the wafer temperature to room temperature in the RTP chamber. 제1항에 있어서, 상기 O2스터핑은 500 내지 700℃ 온도에서 실시되는 것을 특징으로 하는 반도체 소자의 장벽 금속 형성방법.The method of claim 1, wherein the O 2 stuffing is performed at a temperature of 500 to 700 ° C. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950066011A 1995-12-29 1995-12-29 Barrier metal forming method of semiconductor device KR0171948B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950066011A KR0171948B1 (en) 1995-12-29 1995-12-29 Barrier metal forming method of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950066011A KR0171948B1 (en) 1995-12-29 1995-12-29 Barrier metal forming method of semiconductor device

Publications (2)

Publication Number Publication Date
KR970052455A true KR970052455A (en) 1997-07-29
KR0171948B1 KR0171948B1 (en) 1999-03-30

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KR1019950066011A KR0171948B1 (en) 1995-12-29 1995-12-29 Barrier metal forming method of semiconductor device

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100275728B1 (en) * 1998-02-24 2001-01-15 윤종용 Method for manufacturing barrier metal layer of semiconductor device and manufacturing method of metal interconnect using the same

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100275728B1 (en) * 1998-02-24 2001-01-15 윤종용 Method for manufacturing barrier metal layer of semiconductor device and manufacturing method of metal interconnect using the same
US6297153B1 (en) 1998-02-24 2001-10-02 Samsung Electronics Co., Ltd. Method of manufacturing barrier metal film of semiconductor device and method of manufacturing metal interconnection film of semiconductor device using the same

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Publication number Publication date
KR0171948B1 (en) 1999-03-30

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