KR970052136A - Method for manufacturing resistance by ion implantation on semi-insulating gallium arsenide substrate - Google Patents

Method for manufacturing resistance by ion implantation on semi-insulating gallium arsenide substrate Download PDF

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Publication number
KR970052136A
KR970052136A KR1019950053679A KR19950053679A KR970052136A KR 970052136 A KR970052136 A KR 970052136A KR 1019950053679 A KR1019950053679 A KR 1019950053679A KR 19950053679 A KR19950053679 A KR 19950053679A KR 970052136 A KR970052136 A KR 970052136A
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South Korea
Prior art keywords
semiconductor substrate
resistor
ions
forming
resistance
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KR1019950053679A
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Korean (ko)
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KR0169830B1 (en
Inventor
박문평
이태우
송기문
박성호
Original Assignee
양승택
한국전자통신연구원
이준
한국전기통신공사
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Priority to KR1019950053679A priority Critical patent/KR0169830B1/en
Publication of KR970052136A publication Critical patent/KR970052136A/en
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Publication of KR0169830B1 publication Critical patent/KR0169830B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/6631—Bipolar junction transistors [BJT] with an active layer made of a group 13/15 material
    • H01L29/66318—Heterojunction transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/73—Bipolar junction transistors
    • H01L29/737—Hetero-junction transistors
    • H01L29/7371—Vertical transistors

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Bipolar Transistors (AREA)

Abstract

본 발명은 이종접합 트랜지스터의 반절연성 갈륨비소 기판의 소정부분에 실리콘 이온을 주입하여 저항을 제조하는 방법에 관한 것으로서, 이종접합 바이폴라 트랜지스터를 이용하여 수동소자의 저항을 제작하는 집적회로의 공정에 있어서, 반절연성 갈륨비소로 이루어진 반도체기판 상부의 소정 부분에 정렬 표시부(Align Mark)를 형성하는 제1과정과, 정렬 표시부를 기준으로 하여 반도체기판 상에 소정 부분을 노출시키는 감광막을 형성하는 제2과정과, 반도체기판의 노출된 부분에 Si이온을 주입하고 감광막을 제거하는 제3과정과, 반도체기판의 상부 및 하부의 표면에 절연막을 형성하는 제4과정 및 주입된 Si이온을 활성화시켜 저항을 형성하는 제5과정을 포함하여 이루어져, 반도체 기판의 소정의 영역에 Si이온을 주입하는 간단한 공정과정을 통해서 임의의 저항값을 갖는 저항을 제조할 수 있다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a resistor by implanting silicon ions into a predetermined portion of a semi-insulating gallium arsenide substrate of a heterojunction transistor, and in the process of an integrated circuit fabricating a resistor of a passive device using a heterojunction bipolar transistor. And a first process of forming an alignment mark on a predetermined portion of the semiconductor substrate made of semi-insulating gallium arsenide, and a second process of forming a photosensitive film exposing a predetermined portion on the semiconductor substrate based on the alignment display portion. And a third process of injecting Si ions into the exposed portion of the semiconductor substrate and removing the photoresist, a fourth process of forming an insulating film on the upper and lower surfaces of the semiconductor substrate, and activating the implanted Si ions to form a resistance. Including a fifth process, through a simple process of implanting Si ions into a predetermined region of the semiconductor substrate A resistor having any resistance value can be produced.

Description

반절연 갈륨비소 기판 위에 이온주입에 의한 저항 제조방법Method for manufacturing resistance by ion implantation on semi-insulating gallium arsenide substrate

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 (a)∼(d)는 본 발명에 따른 제조공정을보여주는 단면도.2 is a cross-sectional view showing a manufacturing process according to the present invention (a) to (d).

Claims (3)

이종접합 바이폴라 트랜지스터를 이용하여 수동소자인 저항을 제작하는 집적회로의 공정에 있어서, 반절연성 갈륨비소로 이루어진 반도체기판 상부의 소정 부분에 정렬 표시부(Align Mark)를 형성하는 제1과정과; 상기 정렬 표시부를 기준으로 하여 반도체기판 상에 소정 부분을 노출시키는 감광막을 형성하는 제2과정과; 상기 반도체기판의 노출된 부분에 Si 이온을 주입하고 감광막을 제거하는 제3과정과; 상기 반도체기판의 상부 및 하부의 표면에 절연막을 형성하는 제4과정 및 주입된 Si 이온을 활성화시켜 저항을 형성하는 제5과정을 포함하여 이루어져 상기 부콜렉터층부터 에미터캡층까지 에피성장과정에서 정렬 표시부의 패턴이동이 발생하지 않는 것을 특징으로 하는 이종접합 트랜지스터의 저항의 제조방법.An integrated circuit for fabricating a resistor, which is a passive element, using a heterojunction bipolar transistor, comprising: a first process of forming an alignment mark on a predetermined portion of a semiconductor substrate made of semi-insulating gallium arsenide; A second process of forming a photosensitive film exposing a predetermined portion on the semiconductor substrate based on the alignment display unit; A third step of injecting Si ions into the exposed portion of the semiconductor substrate and removing the photoresist film; And a fourth process of forming an insulating film on the upper and lower surfaces of the semiconductor substrate and a fifth process of activating the implanted Si ions to form a resistor, thereby aligning in the epitaxial growth process from the sub-collector layer to the emitter cap layer. A method of manufacturing a resistance of a heterojunction transistor, characterized in that no pattern shift occurs in the display portion. 제1항에 있어서, 상기 제2과정의 감광막의 폭과 길이를 조절함으로써 임의의 저항값을 갖는 저항을 제조할 수 있는 것을 특징으로 하는 이종접합 트랜지스터의 저항의 제조방법.The method of manufacturing a resistor of a heterojunction transistor according to claim 1, wherein a resistor having an arbitrary resistance value can be manufactured by adjusting the width and length of the photosensitive film of the second step. 제1항에 있어서, 상기 제3과정의 이온주입 공정시 가속에너지와 이온양을 조절함으로써 임의의 저항값을 갖는 저항을 제조할 수 있는 것을 특징으로 하는 이종접합 트랜지스터의 저항의 제조방법.The method of manufacturing a resistance of a heterojunction transistor according to claim 1, wherein a resistance having an arbitrary resistance value can be manufactured by adjusting the acceleration energy and the amount of ions during the ion implantation process of the third step. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950053679A 1995-12-21 1995-12-21 Method for manufacturing resistor by ion implantation on semi-insulating gaas substrate KR0169830B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950053679A KR0169830B1 (en) 1995-12-21 1995-12-21 Method for manufacturing resistor by ion implantation on semi-insulating gaas substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950053679A KR0169830B1 (en) 1995-12-21 1995-12-21 Method for manufacturing resistor by ion implantation on semi-insulating gaas substrate

Publications (2)

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KR970052136A true KR970052136A (en) 1997-07-29
KR0169830B1 KR0169830B1 (en) 1999-02-18

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100296705B1 (en) * 1997-10-24 2001-08-07 오길록 Method for fabricating integrated circuit using hetero-junction bipolar transistor

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100296705B1 (en) * 1997-10-24 2001-08-07 오길록 Method for fabricating integrated circuit using hetero-junction bipolar transistor

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