KR930024161A - Semiconductor integrated circuit device and manufacturing method thereof - Google Patents

Semiconductor integrated circuit device and manufacturing method thereof Download PDF

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Publication number
KR930024161A
KR930024161A KR1019930009283A KR930009283A KR930024161A KR 930024161 A KR930024161 A KR 930024161A KR 1019930009283 A KR1019930009283 A KR 1019930009283A KR 930009283 A KR930009283 A KR 930009283A KR 930024161 A KR930024161 A KR 930024161A
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region
well region
well
impurity diffusion
type impurity
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KR1019930009283A
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Korean (ko)
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유스케 코야마
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사또오 후미오
가부시기가이샤 도시바
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Publication of KR930024161A publication Critical patent/KR930024161A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/102—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including bipolar components
    • H01L27/1022—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including bipolar components including bipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823493—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8248—Combination of bipolar and field-effect technology
    • H01L21/8249—Bipolar and MOS technology
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0928—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors comprising both N- and P- wells in the substrate, e.g. twin-tub

Abstract

본 발명은 고정밀도의 소자가 형성된 신뢰성이 높은 반도체 집적회로 장치를 제공하는 동시에, 간략화된 공정으로 고수율, 저코스트의 제조방법을 제공하기 위한 것이다. 본 발명에서는 반도체기판(1)의 N웰(3)에 형성된 바이폴라 트랜지스터의 베이스 영역(72)과 에미터 영역(81)과의 경계상에 필드산화막(4)을 형성한다. 또 베이스영역(72)과 P웰(2)의 소자분리 펀치스루 내압의 향상을 도모하는 P형 불순물 확산 영역(71)을 동일 마스크를 사용하는 1공정으로 형성한다.The present invention is to provide a highly reliable semiconductor integrated circuit device in which a high precision element is formed, and at the same time, to provide a high yield, low cost manufacturing method in a simplified process. In the present invention, the field oxide film 4 is formed on the boundary between the base region 72 and the emitter region 81 of the bipolar transistor formed in the N well 3 of the semiconductor substrate 1. In addition, the P-type impurity diffusion region 71 is formed in one step using the same mask to improve the breakdown through-hole withstand voltage between the base region 72 and the P well 2.

Description

반도체 집적회로 장치 및 그 제조방법Semiconductor integrated circuit device and manufacturing method thereof

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 본 발명의 제1실시예의 반도체 집적회로 장치의 제조공정 단면도, 제2도는 본 발명의 제1실시예의 반도체 집적회로 장치의 제조공정 단면도, 제3도는 본 발명의 제1실시예의 반도체 집적회로 장치의 제조공정 단면도.1 is a cross sectional view of the semiconductor integrated circuit device of the first embodiment of the present invention, FIG. 2 is a cross sectional view of the semiconductor integrated circuit device of the first embodiment of the present invention, and FIG. 3 is a semiconductor integrated circuit of the first embodiment of the present invention. Manufacturing process section of circuit device.

Claims (6)

반도체기판(1)과, 상기 반도체기판에 형성된 웰 영역(3)과, 적어도 상기 웰 영역의 인접하는 다른 영역과의 경계상 및 상기 웰영역의 소정의 영역상의 형성에 필드산화막(4)과, 상기 웰 영역에 형성되고, 이 웰 영역에 형성되는 바이폴라 트랜지스트의 베이스가 되는 제1의 불순물 확산 영역(72)과, 상기 제1의 불순물 확산 영역내에 그 표면에 노출되도록 형성되고, 상기 웰 영역의 소정의 영역상 및 상기 웰 영역의 인접하는 다른 영역과의 경계상에 형성되는 필드산화막에 의하여 에워싸이며, 상기 바이폴라 트랜지스트의 에미터 영역이 되는 제2의 불순물 확산 영역(81)을 구비하는 것을 특징으로 하는 반도체 직접회로 장치.The field oxide film 4 is formed on the boundary between the semiconductor substrate 1, the well region 3 formed on the semiconductor substrate, at least on another boundary of the well region, and on a predetermined region of the well region; A first impurity diffusion region 72 formed in the well region and serving as a base of a bipolar transistor formed in the well region, and exposed to the surface of the first impurity diffusion region in the first impurity diffusion region; And a second impurity diffusion region 81 surrounded by a field oxide film formed on a predetermined region of the well region and on a boundary between other regions adjacent to the well region and serving as an emitter region of the bipolar transistor. Semiconductor integrated circuit device, characterized in that. 반도체기판(1)과, 상기 반도체기판에 형성된 P웰 영역(2)과, 상기 반도체기판에 형성된 N웰 영역(3)과, 적어도 상기 양 웰영역의 경계상, 상기 N웰 영역의 소정의 영역 및 P웰 영역상에 형성된 필드산화막(4)과, 상기 P웰 영역에 형성되고, 적어도 상기 필드산화막의 상기 P웰 영역상에 형성된 부분의 아래에 형성된 제1의 P형 불순물 확산 영역과, 상기 N웰 영역에 형성되고, 이 N웰 영역에 형성되는 비이폴라 트랜지스터의 베이스가 되는 제2의 P형 불순물 확산영역(72)과, 상기 제2의 P형 불순물 확산 영역내에 그 표면이 노출되도록 형성되고, 상기 N웰 영역의 소정의 영역상 및 상기 양 웰영역의 경계상에 형성되는 필드산화막에 의하여 에워싸이며, 상기 바이폴라 트랜지스트의 에미터가 되는 N형 불순물 확산 영역(81)을 구비하고, 상기 제1의 P형 불순물 농도와의 합과 동일하거나 또는 상기 제2의 P형 불순물 확산 영역의 P형 불순물 농도보다 크고 상기 합보다 작은 것을 특징으로 하는 반도체 집적회로 장치.A semiconductor substrate 1, a P well region 2 formed on the semiconductor substrate, an N well region 3 formed on the semiconductor substrate, and a predetermined region of the N well region on at least the boundary between the two well regions. And a field oxide film 4 formed on the P well region, a first P-type impurity diffusion region formed in the P well region and formed under at least a portion formed on the P well region of the field oxide film; A second P-type impurity diffusion region 72 formed in the N well region and serving as a base of the non-polar transistor formed in the N well region, and a surface thereof exposed in the second P-type impurity diffusion region. And an N-type impurity diffusion region 81 which is surrounded by a field oxide film formed on a predetermined region of the N well region and on a boundary between the both well regions and becomes an emitter of the bipolar transistor. And the first P-type impurity concentration Equal to the sum or to the second larger than the P-type impurity concentration in the P-type impurity diffusion region of the second semiconductor integrated circuit device, which is smaller than the sum. 반도체기판(1)의 표면영역에 선택적으로 불순물을 확산하여 P웰영역(2)을 형성하는 공정과, 상기 반도체 판의 표면 영역에 선택적으로 불순물을 확산하여 N웰 영역(3)을 형성하는 공정과, 적어도 상기 양 웰영역의 경계상 및 상기 P웰 영역의 소정의 영역상에 필드산화막(4)을 형성하는 공정과, 적어도 상기 P웰 영역상의 상기 필드 산화막과 상기 N웰 영역의 소정의 영역을 노출시키는 마스크(5)를 반도체기판상에 형성하는 공정과, 상기 마스크를 개재하여 상기 반도체기판에 불순물(6)을 이온주입하는 공정과, 상기 이온주입한 불순물을 열확산하여 상기 P웰 영역에 형성되고, 적어도 상기 필드산화막의 상기 P웰 영역상에 형성된 부분의 아래에 형성된 제1의 P형 불순물 확산 영역(71) 및, 상기 N웰 영역에 형성된 제2의 P형 불순물 확산 영역(72)을 형성하는 공정과, 상기 제2의 P형 불순물 확산 영역내에 노출되도록 N형 불순물 확산 영역(81)을 형성하는 공정을 구비하는 것을 특징으로 하는 반도체 집적회로 장치의 제조방법.Selectively forming impurities in the surface region of the semiconductor substrate 1 to form the P well region 2, and selectively forming impurities in the surface region of the semiconductor substrate to form the N well region 3; And forming a field oxide film 4 on at least the boundary of both well regions and on a predetermined region of the P well region, and at least a predetermined region of the field oxide film and the N well region on the P well region. Forming a mask 5 on the semiconductor substrate, exposing the impurities 6 to the semiconductor substrate through the mask, and thermally diffusing the ion implanted impurities into the P well region. A first P-type impurity diffusion region 71 formed below at least a portion formed on the P well region of the field oxide film and a second P-type impurity diffusion region 72 formed in the N well region Ball forming And a method for fabricating a semiconductor integrated circuit device characterized by comprising the step of forming the N-type impurity diffusion region 81 so as to be exposed in the P-type impurity diffusion region of the second. 반도체기판(1)의 표면영역에 선택적으로 불순물을 확산하여 P웰 영역(2)을 형성하는 공정과, 상기 반도체기판의 표면영역에 선택적으로 불순물을 확산하여 N웰 영역(3)을 형성하는 공정과, 적어도 상기 양 웰영역의 경계상, 상기 N웰 영역 및 P웰 영역의 소정의 영역상에 필드산화막(4)을 형성하는 공정과, 적어도 상기 P웰 영역상의 상기 필드산화막과 상기 N웰 영역의 소정의 영역을 노출시키는 마스크(5)를 상기 반도체기판 상에 형성하는 공정과, 상기 마스크를 개재하여 상기 반도체기판에 불순물(6)을 이온주입하는 공정과, 상기 이온주입된 불순물을 열 확산하여 상기 웰 영역에 형성되고, 적어도 상기 필드산화막의 상기 P웰 영역상에 형성된 부분의 아래에 형성된 제1의 형 불순물 확산 영역(71) 및 상기 N웰 영역에 형성된 제2의 P형 불순물 확산 영역(72)을 형성하는 공정과, 상기 제2의 불순물 확산 영역내에 그 표면이 노출되도록 상기 N웰 영역의 소정의 영역상 및 상기 양 웰영역과 경계상에 형성되는 필드산화막에 위하여 에워싸인 N형 불순물 확산 영역(81)을 형성하는 공정을 구비한 것을 특징으로 하는 반도체 집적회로 장치의 제조방법.Selectively diffusing impurities into the surface region of the semiconductor substrate 1 to form the P well region 2, and selectively diffusing impurities into the surface region of the semiconductor substrate to form the N well region 3; And forming a field oxide film 4 on at least the boundary between the two well regions and on a predetermined region of the N well region and the P well region, and at least the field oxide film and the N well region on the P well region. Forming a mask (5) on the semiconductor substrate that exposes a predetermined region of the substrate, ion implanting the impurities (6) into the semiconductor substrate through the mask, and thermally diffusing the ion implanted impurities And a first type impurity diffusion region 71 formed below the portion formed on the P well region of the field oxide film and a second P-type impurity diffusion region formed on the N well region. (72) And an N-type impurity diffusion region surrounded by a field oxide film formed on a predetermined region of the N well region and on the boundary between the both well regions so that the surface thereof is exposed in the second impurity diffusion region. 81) forming a semiconductor integrated circuit device. 제3항에 있어서, 상기 N웰 영역에는 바이폴라 트랜지스터를 갖는 기준전위 발새생회로를 형성하고, 상기 P웰 영역에는 DRAM 메모리셀을 형성하는 것을 특징으로 하는 반도체 집적회로 장치의 제조방법.4. The method of claim 3, wherein a reference potential generation circuit having a bipolar transistor is formed in the N well region, and a DRAM memory cell is formed in the P well region. 제3항에 있어서, 상기 제1의 P형 불순물 확산 영역이 채널 스토퍼로서 사용되는 것을 특징으로 하는 반도체 집적회로 장치의 제조방법.4. A method according to claim 3, wherein the first P-type impurity diffusion region is used as a channel stopper. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019930009283A 1992-05-30 1993-05-27 Semiconductor integrated circuit device and manufacturing method thereof KR930024161A (en)

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JP92-163724 1992-05-30
JP4163724A JPH05335325A (en) 1992-05-30 1992-05-30 Semiconductor integrated circuit device and its manufacture

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JPH05335325A (en) 1993-12-17

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