KR970053004A - High resistance manufacturing method using sub-collector layer of heterojunction transistor - Google Patents

High resistance manufacturing method using sub-collector layer of heterojunction transistor Download PDF

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KR970053004A
KR970053004A KR1019950053680A KR19950053680A KR970053004A KR 970053004 A KR970053004 A KR 970053004A KR 1019950053680 A KR1019950053680 A KR 1019950053680A KR 19950053680 A KR19950053680 A KR 19950053680A KR 970053004 A KR970053004 A KR 970053004A
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South Korea
Prior art keywords
sub
collector layer
high resistance
forming
layer
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KR1019950053680A
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Korean (ko)
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KR0161198B1 (en
Inventor
박문평
이태우
송기문
박성호
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양승택
한국전자통신연구원
이준
한국전기통신공사
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Priority to KR1019950053680A priority Critical patent/KR0161198B1/en
Publication of KR970053004A publication Critical patent/KR970053004A/en
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Publication of KR0161198B1 publication Critical patent/KR0161198B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/66242—Heterojunction transistors [HBT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0821—Collector regions of bipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45—Ohmic electrodes
    • H01L29/452—Ohmic electrodes on AIII-BV compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/73—Bipolar junction transistors
    • H01L29/737—Hetero-junction transistors
    • H01L29/7371—Vertical transistors

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Bipolar Transistors (AREA)

Abstract

본 발명은 이종접합 트랜지스터의 부콜렉터층을 이용한 고저항의 제조방법에 관한 것으로서, 반절연성 갈륨비소로 이루어진 반도체기판 상부의 부콜렉터층 상부에 저항을 형성하기 위한 소정의 영역을 노출시키는 감광막을 형성하는 제 1 과정과, 상기 부콜렉터층의 노출된 부분에 B+이온을 주입한 후, 결정이 파괴되지 않은 부콜렉터층을 이용하여 저항을 형성하는 제 2 과정 및 상기 감광막을 제거한 후, 리프트 오프공정에 의해 저항 금속(Ohmic Metal)을 형성하는 제 3 과정을 포함하여 이루어져, 반절연성 갈륨비소 기판상부의 부콜렉터층에 B+이온을 주입하는 간단한 공정과정을 통해서 결정이 파괴되지 않은 부콜렉터층을 이용하여 임의의 높은 저항값을 갖는 고저항을 제조할 수 있다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a high resistance using a sub-collector layer of a heterojunction transistor, wherein a photoresist film is formed to expose a predetermined region for forming a resistance on the sub-collector layer on a semiconductor substrate made of semi-insulating gallium arsenide. After the first step of injecting, the B + ion is injected into the exposed portion of the sub-collector layer, the second process of forming a resistance using the sub-collector layer is not destroyed, and the photosensitive film is removed, and then lift-off Including a third process of forming a resistive metal (Ohmic Metal) by the process, the sub-collector layer is not destroyed the crystal through a simple process of implanting B + ions into the sub-collector layer on the semi-insulating gallium arsenide substrate It is possible to manufacture a high resistance having an arbitrary high resistance value by using a.

Description

이종접합 트랜지스터의 부콜렉터층을 이용한 고저항 제조방법High resistance manufacturing method using sub-collector layer of heterojunction transistor

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 (a)∼(c)는 본 발명에 따른 제조공정을 보여주는 단면도.2 is a cross-sectional view showing a manufacturing process according to the present invention (a) to (c).

Claims (2)

이종접합 바이폴라 트랜지스터를 이용하여 수동소자인 저항을 제작하는 집적회로의 공정에 있어서, 반절연성 갈륨비소 기판위의 부콜렉터층 상부에 저항이 형성되기 위한 소정의 영역을 노출시키는 감광막을 형성하는 제 1 과정과, 상기 부콜렉터층의 노출된 부분에 B+이온을 주입한 후, 결정이 파괴되지 않은 부콜렉터층을 이용하여 저항을 형성하는 제 2 과정 및 상기 감광막을 제거한 후 리프트 오프공정에 의해 저항 금속(Ohmic Metal)을 형성하는 제 3 과정을 포함하여 이루어지는 것을 특징으로 하는 이종접합 트랜지스터의 부콜렉터층을 이용한 고저항의 제조방법.In an integrated circuit process for fabricating a resistor, which is a passive element, using a heterojunction bipolar transistor, a first photosensitive film is formed that exposes a predetermined region for forming a resistor on the subcollector layer on a semi-insulating gallium arsenide substrate. And a second process of forming a resistor using a subcollector layer in which crystals are not destroyed after implanting B + ions into an exposed portion of the subcollector layer, and then removing the photosensitive layer and then performing a lift off process. A method of manufacturing high resistance using a sub-collector layer of a heterojunction transistor, comprising a third step of forming an ohmic metal. 제1항에 있어서, 상기 제 2 과정의 이온주입 공정시 감광막의 두께를 조절함으로써 상기 BB+이온에 의해 저항의 오믹 금속영역의 결정이 파괴되지 않도록 하는 것을 특징으로 하는 이종접합 트랜지스터의 부콜렉터층을 이용한 고저항의 제조방법.The sub-collector layer of the heterojunction transistor according to claim 1, wherein the thickness of the photoresist film is adjusted during the ion implantation process of the second process so that the crystal of the ohmic metal region of the resistance is not destroyed by the BB + ions. High resistance manufacturing method using. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950053680A 1995-12-21 1995-12-21 Method for manufacturing resistor having high resistance by using subcollector layer of heterojunction transistor KR0161198B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950053680A KR0161198B1 (en) 1995-12-21 1995-12-21 Method for manufacturing resistor having high resistance by using subcollector layer of heterojunction transistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950053680A KR0161198B1 (en) 1995-12-21 1995-12-21 Method for manufacturing resistor having high resistance by using subcollector layer of heterojunction transistor

Publications (2)

Publication Number Publication Date
KR970053004A true KR970053004A (en) 1997-07-29
KR0161198B1 KR0161198B1 (en) 1999-02-01

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20020031722A (en) * 2000-10-23 2002-05-03 김우진 Structure and method for heterojunction bipola transistor

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20020031722A (en) * 2000-10-23 2002-05-03 김우진 Structure and method for heterojunction bipola transistor

Also Published As

Publication number Publication date
KR0161198B1 (en) 1999-02-01

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