KR970004058A - Manufacturing method of highly integrated bipolar transistor - Google Patents

Manufacturing method of highly integrated bipolar transistor Download PDF

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Publication number
KR970004058A
KR970004058A KR1019950017238A KR19950017238A KR970004058A KR 970004058 A KR970004058 A KR 970004058A KR 1019950017238 A KR1019950017238 A KR 1019950017238A KR 19950017238 A KR19950017238 A KR 19950017238A KR 970004058 A KR970004058 A KR 970004058A
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KR
South Korea
Prior art keywords
oxide
emitter
collector
mask
bipolar transistor
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Application number
KR1019950017238A
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Korean (ko)
Inventor
황준
Original Assignee
김주용
현대전자산업 주식회사
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Application filed by 김주용, 현대전자산업 주식회사 filed Critical 김주용
Priority to KR1019950017238A priority Critical patent/KR970004058A/en
Publication of KR970004058A publication Critical patent/KR970004058A/en

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Abstract

본 발명은 고집적화를 이룰 수 있는 바이폴라 트랜지스터 제조방법에 관한 것이다.The present invention relates to a bipolar transistor manufacturing method capable of high integration.

이와 같은 본 발명의 고집적 바이폴라 트랜지스터의 제조방법은 반도체 기판위에 n형의 이온주입을 실시하여 n+형의 콜렉터를 형성하는 공정과, 콜렉터가 형성된 기판위에 산화물을 증착하고 마스크 및 식각을 통하여 상기 n+의 콜렉터의 소정부분의 상부가 노출되도록 두 부분의 산화물을 식각하는 공정과, 산화물의 구멍이 형성된 부분에 선택적인 에피택셜 성장시키는 공정과, 성장된 에피택셜 실리콘 표면을 평탄화 하여 p-형 불순물을 이온주입하는 공정과, 이온주입된 에피택셜층중 스텝이 형성된 부분의 위에 폴리실리콘을 성막하여 이미터 패턴을 형성하고, 이미터 폴리실리콘의 측단부에 스페이서 산화물을 형성한 다음 그 형성된 이미터부분을 마스크로 하여 P+이온을 주입하는 공정을 포함하는 것을 특징으로 한다.Such a method for manufacturing a highly integrated bipolar transistor of the present invention comprises the steps of forming an n + type collector by implanting an ion of n type on a semiconductor substrate, depositing an oxide on the substrate on which the collector is formed, and forming the n through mask and etching. Etching two portions of the oxide so that the upper portion of the collector of + is exposed, selectively epitaxially growing the oxide hole and planarizing the grown epitaxial silicon surface to form a p-type impurity Ion-implanted, polysilicon is formed on the stepped portion of the ion-implanted epitaxial layer to form an emitter pattern, a spacer oxide is formed on the side end of the emitter polysilicon, and then the formed emitter And implanting P + ions using the portion as a mask.

Description

고집적 바이폴라 트랜지스터의 제조방법Manufacturing method of highly integrated bipolar transistor

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

첨부한 도면은 본 발명 바이폴라 트랜지스터의 제조과정을 설명하기 위한 공정 흐름도.The accompanying drawings are a process flow diagram for explaining the manufacturing process of the bipolar transistor of the present invention.

Claims (3)

반도체 기판위에 n형의 이온주입을 실시하여 n+형의 콜렉터를 형성하는 공정과, 콜렉터가 형성된 기판위에 산화물을 증착하고 마스크 및 식각을 통하여 상기 n+의 콜렉터의 소정부분의 상부가 노출되도록 두 부분의 산화물을 식각하는 공정에 의해서 구멍이 형성된 부분에 선택적인 에피택셜 성장 실리콘 성장시키는 공정과, 성장된 에피택셜 실리콘 표면을 평판화 하여 p-형 불순물을 이온주입하는 공정과, 이온주입된 에피택셜층중 스탭이 형성된 부분의 위에 폴리실리콘을 성막하여 이미터 패턴을 형성하고, 상기 이미터 폴리실리콘의 측단부에 스페이서 산화물을 형성한 다음 그 형성된 이미터부분을 마스크로 하여 p+이온을 주입하는 공정을 포함하는 것을 특징으로 하는 고집적 바이폴라 트랜지스터 제조방법.Forming an n + type collector by performing n type ion implantation on a semiconductor substrate, depositing an oxide on the substrate on which the collector is formed, and exposing an upper portion of the predetermined part of the collector of n + through a mask and etching A process of selectively growing epitaxially grown silicon in a hole formed by a process of etching an oxide of the portion, a process of ionizing p-type impurities by flattening the grown epitaxial silicon surface, and ion implanted epi Polysilicon is formed on the stepped portion of the tactical layer to form an emitter pattern, a spacer oxide is formed on the side end of the emitter polysilicon, and p + ions are implanted using the formed emitter portion as a mask. A method for manufacturing a highly integrated bipolar transistor, comprising the step of: 제1항에 있어서, 상기 산화물의 식각되는 두 부분중 하나는 2회의 마스크 막식각을 통하여 스텝을 가지도록 형성하는 것을 특징으로 하는 고집적 바이폴라 트랜지스터 제조방법.The method of claim 1, wherein one of the two etched portions of the oxide is formed to have a step through two mask film etching processes. 제1항에 있어서, 상기 이미터 형성공정중 스페이서 산화물의 일측단 폭은 0.1~0.15㎛ 범위 이내인 것을 특징으로 하는 고집적 바이폴라 트랜지스터의 제조방법.The method of claim 1, wherein the width of one end of the spacer oxide in the emitter forming process is within a range of 0.1 μm to 0.15 μm. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950017238A 1995-06-24 1995-06-24 Manufacturing method of highly integrated bipolar transistor KR970004058A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950017238A KR970004058A (en) 1995-06-24 1995-06-24 Manufacturing method of highly integrated bipolar transistor

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Application Number Priority Date Filing Date Title
KR1019950017238A KR970004058A (en) 1995-06-24 1995-06-24 Manufacturing method of highly integrated bipolar transistor

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KR970004058A true KR970004058A (en) 1997-01-29

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