KR970051166A - Semiconductor memory device - Google Patents

Semiconductor memory device Download PDF

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Publication number
KR970051166A
KR970051166A KR1019950059457A KR19950059457A KR970051166A KR 970051166 A KR970051166 A KR 970051166A KR 1019950059457 A KR1019950059457 A KR 1019950059457A KR 19950059457 A KR19950059457 A KR 19950059457A KR 970051166 A KR970051166 A KR 970051166A
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KR
South Korea
Prior art keywords
column
memory array
array groups
memory
sub
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Application number
KR1019950059457A
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Korean (ko)
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KR100350700B1 (en
Inventor
장현순
오승철
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김광호
삼성전자 주식회사
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Priority to KR1019950059457A priority Critical patent/KR100350700B1/en
Publication of KR970051166A publication Critical patent/KR970051166A/en
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Publication of KR100350700B1 publication Critical patent/KR100350700B1/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/12—Group selection circuits, e.g. for memory block selection, chip selection, array selection
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G11C5/025—Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/10—Decoders
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408—Address circuits
    • G11C11/4087—Address decoders, e.g. bit - or word line decoders; Multiple line decoders

Abstract

1. 청구범위에 기재된 발명이 속하는 기술 분야1. TECHNICAL FIELD OF THE INVENTION

본 발명은 반도체 메모리 장치에 관한 것이다.The present invention relates to a semiconductor memory device.

2. 발명이 해결하려고 하는 기술적 과제2. The technical problem to be solved by the invention

본 발명은 불필요한 컬럼디코더를 줄임으로써 레이아웃상의 칩 면적을 축소하는 반도체 메모리 장치를 제공한다.The present invention provides a semiconductor memory device that reduces chip area on a layout by reducing unnecessary column decoders.

3. 발명의 해결방법의 요지3. Summary of Solution to Invention

본 발명은 로우어드레스에 의하여 워드라인을 선택하여 동작시키고 컬럼 어드레스에 의하여 컬럼 프리디코더를 거쳐 컬럼디코더의 출력신호인 컬럼선택라인에의하여 비트라인을 선택하고 메모리 셀을 엑세스하여 데이타를 라이트 하거나 리이드 동작을 수행하는 반도체 메모리 장치에 있어서, 서브 메모리 어레이가 두개이상 다수개가 존재하고, 상기 두개 이상 다수개의 서브 메모리 어레이는 다수개의 메모리 어레이 그룹으로 나누어지고, 상기 컬럼선택라인은 서브 메모리 어레이 위에 배치되어 다수개의 서브 메모리 어레이의 비트라인을 제어하며 다수개의 메모리 어레이 그룹으로 나우어진 그룹은 두개의 메모리 어레이 그룹으로 서로 짝을 이루어 동작하며 상기 두개로 짝을 이룬 메모리 어레이 그룹사이에는 컬럼디코더만이 배치되고, 상기 컬럼디코더에는 컬럼선택 라인을 구동하는 구동단이 두개 존재하여 상기 두개의 메모리 어레이 그룹을 각각 제어하며 상기 컬럼디코더를 제어하는 프리디코딩 라인은 양쪽의 컬럼선택라인을 구동하는 구동단을 동시에 제어함을 특징으로 한다.According to the present invention, a word line is selected and operated by a row address, a bit line is selected by a column selection line which is an output signal of a column decoder through a column predecoder by a column address, and a memory cell is accessed to write data or read operations. In the semiconductor memory device for performing the above operation, two or more sub-memory arrays are present, the two or more sub-memory arrays are divided into a plurality of memory array groups, and the column selection lines are arranged on the sub-memory arrays. A group divided into a plurality of memory array groups operates by pairing each other with two memory array groups, and only a column decoder is disposed between the paired memory array groups. remind There are two driving stages for driving the column selection lines in the column decoder to control the two memory array groups, respectively, and the pre-decoding lines for controlling the column decoders control the driving stages for driving both column selection lines. It features.

4. 발명의 중요한 용도4. Important uses of the invention

본 발명은 반도체 메모리 장치에 적합하게 사용된다.The present invention is suitably used for a semiconductor memory device.

Description

반도체 메모리 장치Semiconductor memory device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제2도는 본 발명에 따른 칩내의 컬럼디코더의 배치 구성을 보여주는 블럭도.2 is a block diagram showing the arrangement of a column decoder in a chip according to the present invention.

Claims (2)

로우어드레스에 의하여 워드라인을 선택하여 동작시키고 컬럼어드레스에 의하여 컬럼 프리디코더를 거쳐 컬럼디코더의 출력신호인 컬럼선태라인에 의하여 비트라인을 선택하고 메모리 셀을 액세스하여 데이타를 라이트하거나 리이드 동작을 수행하는 반도체 메모리 장치에 있어서, 서브 메모리 어레이가 두개이상 다수개가 존재하고, 상기 두개이상 다수개의 서브 메모리 어레이는 다수개의 메모리 어레이 그룹으로 나누어지고, 상기 컬럼선택라인은 서브 메모리 어레이 위에 배치되어 다수개의 서브 메모리 어레이의 비트라인을 제어하며 다수개의 메모리 어레이 그룹으로 나우어진 그룹은 두개의 메모리 어레이 그룹으로 서로 짝을 이루어 동작하며 상기 두개의 짝을 이룬 메모리 어레이 그룹사이에는 컬럼디코더만이 배치되고, 상기 컬럼디코더에는 컬럼선택 라인을 구동하는 구동단이 두개 존재하여 상기 두개의 메모리 어레이 그룹을 각각 제어하며 상기 컬럼디코더를 제어하는 프리디코딩 라인은 양쪽의 컬럼선택라인을 구동하는 구동단을 동시에 제어함을 특징으로 하는 반도체 메모리 장치.The word line is selected and operated by the low address, and the bit line is selected by the column selection line which is the output signal of the column decoder through the column predecoder by the column address, and the memory cells are accessed to write or read data. In the semiconductor memory device, there are two or more sub memory arrays, the two or more sub memory arrays are divided into a plurality of memory array groups, and the column selection lines are disposed on the sub memory arrays to provide a plurality of sub memories. A group divided into a plurality of memory array groups that operate on a bit line of an array operates in pairs with two memory array groups, and only a column decoder is disposed between the paired memory array groups, and the column decoder Since there are two driving stages for driving the column selection lines, the two memory array groups are controlled respectively, and the predecoding line for controlling the column decoder controls the driving stages for driving both column selection lines simultaneously. A semiconductor memory device. 로우어드레스 의하여 워드라인을 선택하여 동작시키고 컬럼어드레스에 의하여 컬럼 프리디코더를 거쳐 컬럼디코더의 출력라인인 컬럼선택라인에 의하여 비트라인을 선택하고 메모리 셀을 엑세스하여 데이타를 라이트 하거나 리이드 동작을 수행하는 반도체 메모리 장치에 있어서, 서브 메모리 어레이가 두개이상 다수개가 존재하고, 상기 두개이상 다수개의 서브 메모리 어레이는 다수개의 메모리 어레이 그룹으로 나누어지고, 상기 컬럼선택라인은 서브 메모리 어레이 위에 배치되어 다수개의 서브 메모리 어레이의 비트라인을 제어하며 다수개의 메모리 어레이 그룹으로 나누어진 그룹은 두개의 메모리 어레이 그룹으로 서로 짝을 이루어 동작하며 상기 두개의 짝을 이룬 메모리 어레이 그룹사이에는 컬럼디코더만이 배치되고, 상기 컬럼디코더에는 컬럼선택 라인을 구동하는 구동단이 한개 존재하여 상기 두개의 뱅크 메모리 어레이 그룹을 하나의 구동단으로 제어하며 상기 컬럼디코더에 컬럼선택라인을 구동하여 동시에 제어함을 특징으로 하는 반도체 메모리 장치.A semiconductor that selects and operates a word line by a low address, selects a bit line by a column select line that is an output line of a column decoder through a column predecoder by a column address, and accesses a memory cell to write data or perform a read operation. In the memory device, there are two or more sub memory arrays, wherein the two or more sub memory arrays are divided into a plurality of memory array groups, and the column selection lines are disposed on the sub memory arrays. A group divided into a plurality of memory array groups operates by pairing each other with two memory array groups, and only a column decoder is disposed between the paired memory array groups, and the column decoder is disposed on the column decoder. Driving stage for driving the column select lines is there one by controlling the two-bank memory array group in one of the driving stage and the semiconductor memory device, it characterized in that the control drives the column select line in the column decoder at the same time. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950059457A 1995-12-27 1995-12-27 Semiconductor memory apparatus KR100350700B1 (en)

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KR1019950059457A KR100350700B1 (en) 1995-12-27 1995-12-27 Semiconductor memory apparatus

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20030035805A (en) * 2001-10-26 2003-05-09 미쓰비시덴키 가부시키가이샤 Semiconductor memory device allowing high density structure or high performance
KR100574242B1 (en) * 1997-09-29 2006-07-21 지멘스 악티엔게젤샤프트 Space-efficient semiconductor memory having hierarchical column select line architecture

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100772104B1 (en) 2006-04-11 2007-11-01 주식회사 하이닉스반도체 Semiconductor memory device for bank area security

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100574242B1 (en) * 1997-09-29 2006-07-21 지멘스 악티엔게젤샤프트 Space-efficient semiconductor memory having hierarchical column select line architecture
KR20030035805A (en) * 2001-10-26 2003-05-09 미쓰비시덴키 가부시키가이샤 Semiconductor memory device allowing high density structure or high performance

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