KR890017705A - Semiconductor memory device - Google Patents

Semiconductor memory device Download PDF

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Publication number
KR890017705A
KR890017705A KR1019890005800A KR890005800A KR890017705A KR 890017705 A KR890017705 A KR 890017705A KR 1019890005800 A KR1019890005800 A KR 1019890005800A KR 890005800 A KR890005800 A KR 890005800A KR 890017705 A KR890017705 A KR 890017705A
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KR
South Korea
Prior art keywords
memory cell
semiconductor memory
memory device
mode
semiconductor
Prior art date
Application number
KR1019890005800A
Other languages
Korean (ko)
Inventor
료이찌 구리하라
Original Assignee
마다 가쓰시게
가부시기가이샤 히다찌세이사꾸쇼
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 마다 가쓰시게, 가부시기가이샤 히다찌세이사꾸쇼 filed Critical 마다 가쓰시게
Publication of KR890017705A publication Critical patent/KR890017705A/en

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/12—Group selection circuits, e.g. for memory block selection, chip selection, array selection
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/14—Word line organisation; Word line lay-out

Abstract

내용 없음No content

Description

반도체메모리장치Semiconductor memory device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 본원 발명의 일실시예를 나타내는 반도체메모리장치의 블록도. 제2도는 제1도에 나타낸 반도체 메모리장치의 독해동작을 나타내는 타임차트. 제3도는 제1도에 나타낸 반도체메모리장치의 리프레쉬동작을 나타내는 타임챠트.1 is a block diagram of a semiconductor memory device showing one embodiment of the present invention. FIG. 2 is a time chart showing a read operation of the semiconductor memory device shown in FIG. 3 is a time chart showing the refresh operation of the semiconductor memory device shown in FIG.

Claims (7)

메모리셀을 매트릭스형을 배치한 메모리셀어레이를 열(列)방향으로 분할하여 배치한 복수의 메모리셀군과, 이 복수의 메모리셀군의 각각에 대응하여 배설되어 각 메모리셀군중의 특정의 것을 선택하는 메모리셀군선택과, 상기 복수의 메모리셀군 선택선중 선택된 1개를 활성화하는 제1의 모드와 복수개 동시에 활성화하는 제2의 모드의 어느 하나를 취하도록 제어하는 수단을 배설한 것을 특징으로 하는 반도체메모리장치.A plurality of memory cell groups arranged by dividing the memory cell array in which the memory cells are arranged in a matrix form in a column direction; And a means for controlling to take one of a memory cell group selection and a first mode of activating a selected one of the plurality of memory cell group selection lines and a second mode of activating a plurality of simultaneously. Device. 제1항에 있어서, 상기제어수단은 데이터의 기입, 독해동작시에는 상기 제1의 모드를 취하고, 리프레쉬동작시에는 상기 제2의 모드를 취하는 것을 특징으로 하는 반도체메모리장치.2. The semiconductor memory device according to claim 1, wherein said control means takes said first mode when writing and reading data, and takes said second mode when refreshing. 제1항에 있어서, 상기 제어수단은 상기 제2의 모드를 취할 때 상기 메모리셀군선택 전부를 활성화하는 것을 특징으로 하는 반도체메모리장치.The semiconductor memory device according to claim 1, wherein said control means activates all of said memory cell group selections when taking said second mode. 제1항에 있어서, 상기 메모리셀은 다이나믹형 메모리셀인 것을 특징으로 하는 반도체메모리장치.2. The semiconductor memory device according to claim 1, wherein said memory cell is a dynamic memory cell. 제1항에 있어서, 상기 메모리셀은 스태틱형 메모리셀인 것을 특징으로 하는 반도체메모리장치.The semiconductor memory device according to claim 1, wherein the memory cell is a static memory cell. 제1항에 있어서, 상기 메모리셀은 불휘발성메모리셀인 것을 특징으로 하는 반도체메모리장치.The semiconductor memory device according to claim 1, wherein the memory cell is a nonvolatile memory cell. 제1항에 있어서, 상기 메모리셀군을 등분으로 좌우로 분할하도록 중앙에 행(行)디코더를 배치하는 것을 특징으로 하는 반도체메모리장치.2. The semiconductor memory device according to claim 1, wherein a row decoder is arranged at the center so as to divide the memory cell group into equal parts.
KR1019890005800A 1988-05-30 1989-05-01 Semiconductor memory device KR890017705A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP63130121A JPH01300496A (en) 1988-05-30 1988-05-30 Semiconductor memory device
JP63-130121 1988-05-30

Publications (1)

Publication Number Publication Date
KR890017705A true KR890017705A (en) 1989-12-16

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019890005800A KR890017705A (en) 1988-05-30 1989-05-01 Semiconductor memory device

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JP (1) JPH01300496A (en)
KR (1) KR890017705A (en)
DE (1) DE3917558A1 (en)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06195964A (en) * 1992-10-01 1994-07-15 Nec Corp Semiconductor memory
JPH06195966A (en) * 1992-10-01 1994-07-15 Nec Corp Semiconductor memory
JPH07107799B2 (en) * 1992-11-04 1995-11-15 日本電気株式会社 Semiconductor memory device
US6774892B2 (en) 2000-09-13 2004-08-10 Seiko Epson Corporation Display driver IC
JP3640175B2 (en) 2001-04-13 2005-04-20 セイコーエプソン株式会社 Nonvolatile semiconductor memory device
JP3780865B2 (en) 2001-04-13 2006-05-31 セイコーエプソン株式会社 Nonvolatile semiconductor memory device
JP3659205B2 (en) 2001-08-30 2005-06-15 セイコーエプソン株式会社 Nonvolatile semiconductor memory device and driving method thereof
KR100597636B1 (en) * 2004-06-08 2006-07-05 삼성전자주식회사 Phase change Random Access Memory device
JP5315940B2 (en) * 2008-11-06 2013-10-16 日本電気株式会社 Magnetic random access memory

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4747082A (en) * 1984-11-28 1988-05-24 Hitachi Ltd. Semiconductor memory with automatic refresh means
JPS62202399A (en) * 1985-10-04 1987-09-07 Mitsubishi Electric Corp Semiconductor memory

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Publication number Publication date
JPH01300496A (en) 1989-12-04
DE3917558A1 (en) 1989-12-07

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