KR970028586A - Circuit emulation test apparatus - Google Patents
Circuit emulation test apparatus Download PDFInfo
- Publication number
- KR970028586A KR970028586A KR1019950042653A KR19950042653A KR970028586A KR 970028586 A KR970028586 A KR 970028586A KR 1019950042653 A KR1019950042653 A KR 1019950042653A KR 19950042653 A KR19950042653 A KR 19950042653A KR 970028586 A KR970028586 A KR 970028586A
- Authority
- KR
- South Korea
- Prior art keywords
- flip
- flop
- output
- signal
- reset signal
- Prior art date
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- Test And Diagnosis Of Digital Computers (AREA)
Abstract
본 발명은 회로 에뮬레이션 장치를 공개한다. 그 장치는 제1신호와 제2신호를 논리곱하는 제1논리곱과, 제1논리곱의 출력을 클럭입력되는 제2신호의 하강 엣지에서 출력하는 제1플리플롭과, 제1플립플롭의 출력을 외부로부터 클럭입력되는 외부 리셋신호의 상승 엣지에서 출력하는 제2플립플롯과, 외부리셋신호와 제2신호를 논리곱하여 제2플립플롭의 리셋신호로서 출력되는 제2논리곱과, 제2논리곱의 출력과 제2플립플롭의 반전된 출력을 논리곱하여 제1플립플롭의 리셋신호로서 인가하는 제3논리곱과, 및 제2플립플롭의 출력과 소정 시간 지연된 외부리셋신호를 논리합하여 회로의 내부리셋신호로서 출력하는 논리합으로 구성되는 것이 바람직하고, 칩에 입출력 핀의 상태를 에뮬레이션 상태로 세트시키고, 이 상태에서 칩을 시스템으로부터 제거하지 않고 에뮬레이션하여 시스템을 디버깅(dubbing)하거나 테스트할 수 있는 효과가 있다.The present invention discloses a circuit emulation apparatus. The apparatus includes a first logical product for logically multiplying a first signal and a second signal, a first flip-flop for outputting the output of the first logical product at the falling edge of the second signal to be clocked in, and an output of the first flip-flop A second flip plot for outputting the signal at the rising edge of the external reset signal inputted from the outside, a second logical product output as a reset signal of the second flip flop by performing an AND operation on the external reset signal and the second signal, and a second logic A third logical product of the product of the product and the inverted output of the second flip-flop and applied as a reset signal of the first flip-flop, and the output of the second flip-flop and the external reset signal delayed by a predetermined time, It is preferably composed of a logic sum outputted as an internal reset signal, and the state of the input / output pins is set to the emulation state on the chip, and in this state, the chip is emulated without removing the chip from the system, thereby debugging the system. Can be tested or tested.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.
제1도는 본 발명에 의한 회로 에뮬레이션 장치의 회로도이다.1 is a circuit diagram of a circuit emulation apparatus according to the present invention.
제2a~2d도는 제1도에 도시된 입력단자로 인가되는 신호 및 출력단자로 출력되는 신호들의 타이밍도이다.2A to 2D are timing diagrams of signals applied to the input terminal and signals output to the output terminal shown in FIG.
Claims (1)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950042653A KR970028586A (en) | 1995-11-21 | 1995-11-21 | Circuit emulation test apparatus |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950042653A KR970028586A (en) | 1995-11-21 | 1995-11-21 | Circuit emulation test apparatus |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| KR970028586A true KR970028586A (en) | 1997-06-24 |
Family
ID=66588183
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019950042653A KR970028586A (en) | 1995-11-21 | 1995-11-21 | Circuit emulation test apparatus |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR970028586A (en) |
-
1995
- 1995-11-21 KR KR1019950042653A patent/KR970028586A/en not_active Application Discontinuation
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| WITN | Withdrawal due to no request for examination |