KR970024320A - Manufacturing method of stacked capacitor of semiconductor device - Google Patents

Manufacturing method of stacked capacitor of semiconductor device Download PDF

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Publication number
KR970024320A
KR970024320A KR1019950035292A KR19950035292A KR970024320A KR 970024320 A KR970024320 A KR 970024320A KR 1019950035292 A KR1019950035292 A KR 1019950035292A KR 19950035292 A KR19950035292 A KR 19950035292A KR 970024320 A KR970024320 A KR 970024320A
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KR
South Korea
Prior art keywords
conductive layer
insulating film
forming
conductive
side wall
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Application number
KR1019950035292A
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Korean (ko)
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KR0155621B1 (en
Inventor
김창수
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문정환
엘지반도체 주식회사
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Priority to KR1019950035292A priority Critical patent/KR0155621B1/en
Publication of KR970024320A publication Critical patent/KR970024320A/en
Application granted granted Critical
Publication of KR0155621B1 publication Critical patent/KR0155621B1/en

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40Capacitors
    • H01L28/60Electrodes
    • H01L28/75Electrodes comprising two or more layers, e.g. comprising a barrier layer and a metal layer

Abstract

본 발명에 의한 반도체 장치의 적층형 캐패시터 제조방법은 반도체기판상에 제1절연막을 형성시키고, 제 1절연막을 선택식각하여 콘택홀을 형성시키는 단계와, 콘택홀의 측벽에 절연막측벽을 형성시키는 단계와, 콘택홀과 제 1 절연막 위에 제 1도전층을 형성시키고, 제 1도전층 위에 제 2 절연막을 형성시키는 단계와, 제 2절연막과 제 1도전층을 선택 제거하여, 콘택홀영역과 대용되는 제 1전극영역에 제 2절연막과 제 1도전층을 잔류시키는 단계와, 제 2절연막과 제 1도전층 및 제 1절연막 위에 제 2도전층을 형성시키고, 제 2도전층을 이방성 건식식각하여, 제 2절연막 및 제 1도전층 측벽에 도전막측벽을 형성시키는 단계와, 도전막측벽의 측벽프로파일이 곡선이 되도록 도전막측벽을 건식식각하는 단계와, 제 2절연막을 제거하는 단계를 포함하여 이루어진다.A method of manufacturing a stacked capacitor of a semiconductor device according to the present invention comprises the steps of forming a first insulating film on a semiconductor substrate, selectively etching the first insulating film to form a contact hole, and forming an insulating film side wall on the sidewall of the contact hole; Forming a first conductive layer over the contact hole and the first insulating film, forming a second insulating film over the first conductive layer, and selectively removing the second insulating film and the first conductive layer to substitute the contact hole region. Leaving a second insulating film and a first conductive layer in the electrode region, forming a second conductive layer over the second insulating film, the first conductive layer and the first insulating film, and anisotropically dry etching the second conductive layer to form a second Forming a conductive film side wall on the insulating film and the sidewall of the first conductive layer, dry etching the conductive film side wall such that the side wall profile of the conductive film side wall is curved, and removing the second insulating film. The.

Description

반도체 장치의 적층형 캐패시터 제조방법Manufacturing method of stacked capacitor of semiconductor device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제 2 도는 본 발명에 의한 반도체 장치의 적층형 캐패시터 제조방법을 설명하기 위한 도면.2 is a view for explaining a method of manufacturing a stacked capacitor of a semiconductor device according to the present invention.

Claims (4)

반도체 장치의 적층형 캐패시터 제조방법에 있어서, 1) 반도체기판상에 제 1절연막을 형성시키고, 상기 제 1절연막을 선택식각하여 콘택홀을 형성시키는 단계와, 2) 상기 콘택홀의 측벽에 절연막측벽을 형성시키는 단계와, 3) 상기 콘택홀과 상기 제 1절연막 위에 제 1도전층을 형성시키고, 상기 제1도전층 위에 제 2절연막을 형성시키는 단계와, 4) 상기 제 2절연막과 상기 제 1도전층을 선택 제거하여, 상기 콘택홀영역과 대응되는 제 1전극 영역에 상기 제 2절연막과 상기 제 1도전층을 잔류시키는 단계와, 5) 상기 제 2절연막과 상기 제 1 도전층 및 상기 제1 절연막 위에 제 2도전층을 형성시키고, 상기 제 2도전층을 이방성 건식식각하여, 상기 제2절연막 및 상기 제 1도전층 측벽에 도전막측벽을 형성시키는 단계와, 6) 상기 도전막측벽의 측벽프로파일이 곡선이 되도록 상기 도전막측벽을 건식식각하는 단계와, 7) 상기 제 2절연막을 제거하는 단계를 포함하여 이루어지는 반도체 장치의 적층형 캐패시터 제조방법.1. A method of manufacturing a stacked capacitor of a semiconductor device, comprising: 1) forming a first insulating film on a semiconductor substrate, and selectively etching the first insulating film to form a contact hole, and 2) forming an insulating film side wall on a sidewall of the contact hole. 3) forming a first conductive layer on the contact hole and the first insulating layer, and forming a second insulating layer on the first conductive layer, and 4) the second insulating layer and the first conductive layer. Removing the second insulating layer and the first conductive layer in the first electrode region corresponding to the contact hole region; and 5) the second insulating layer, the first conductive layer, and the first insulating layer. Forming a second conductive layer thereon and anisotropically dry etching the second conductive layer to form a conductive film side wall on the sidewalls of the second insulating film and the first conductive layer, and 6) a sidewall profile of the side wall of the conductive film. This curve A step of dry etching the conductive film such that side walls, 7) stacked capacitor The method for manufacturing a semiconductor device comprising the step of removing said second insulating film. 제 1 항에 있어서, 상기 6)단계에서, 상기 도전물질측벽의 건식식각은 CF4화학가스를 포함하는 산화막성 식각가스의 플라즈마 건식식각인 것을 특징으로 하는 반도체 장치의 적층형 캐패시터 제조방법.The method of claim 1, wherein in step 6), the dry etching of the side wall of the conductive material is a plasma dry etching of an oxide film etching gas containing CF 4 chemical gas. 제 2 항에 있어서, 상기 산화막성 식각가스의 플라즈마 건식식각은 식각을 진행시키는 반응실의 압력이 20에서 100mTorr이고, 내부 온도는 20에서 60℃ 사이의 범위의 환경에서, 상기 산화막성 식각가스를 플라즈마로 하기 위한 고주파전력이 160에서 250와트 [W] 범위로 인가되어 실시되는 것을 특징으로 하는 반도체 장치의 적층형 캐패시터 제조방법.The method of claim 2, wherein the plasma dry etching of the oxide film etching gas has a pressure of 20 to 100 mTorr in the reaction chamber for performing etching and an internal temperature of 20 to 60 ° C. A method of manufacturing a stacked capacitor of a semiconductor device, characterized in that the high frequency power for plasma is applied in the range of 160 to 250 watts [W]. 제 1 항에 있어서, 상기 제1도전층 또는 제 2 도전층은 다결정 실리콘, 텅스텐 실리사이드, 산화루테늄(RuOx)계 물질, 백금, 티타늄, 질화티타늄 중의 하나로 형성시키는 것을 특징으로 하는 반도체 장치의 적층형 캐패시터 제조방법.The multilayer capacitor of claim 1, wherein the first conductive layer or the second conductive layer is formed of one of polycrystalline silicon, tungsten silicide, ruthenium oxide (RuOx) -based material, platinum, titanium, and titanium nitride. Manufacturing method. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950035292A 1995-10-13 1995-10-13 Method for manufacturing the stacked type capacitor of semiconductor device KR0155621B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950035292A KR0155621B1 (en) 1995-10-13 1995-10-13 Method for manufacturing the stacked type capacitor of semiconductor device

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Application Number Priority Date Filing Date Title
KR1019950035292A KR0155621B1 (en) 1995-10-13 1995-10-13 Method for manufacturing the stacked type capacitor of semiconductor device

Publications (2)

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KR970024320A true KR970024320A (en) 1997-05-30
KR0155621B1 KR0155621B1 (en) 1998-10-15

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100392850B1 (en) * 2000-12-29 2003-07-28 엘지.필립스 엘시디 주식회사 Liquid Crystal Display Device and Fabricating Method Thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100392850B1 (en) * 2000-12-29 2003-07-28 엘지.필립스 엘시디 주식회사 Liquid Crystal Display Device and Fabricating Method Thereof

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KR0155621B1 (en) 1998-10-15

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