KR970024270A - Method for manufacturing a semiconductor device having a metal-salicide structure - Google Patents

Method for manufacturing a semiconductor device having a metal-salicide structure Download PDF

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Publication number
KR970024270A
KR970024270A KR1019950037202A KR19950037202A KR970024270A KR 970024270 A KR970024270 A KR 970024270A KR 1019950037202 A KR1019950037202 A KR 1019950037202A KR 19950037202 A KR19950037202 A KR 19950037202A KR 970024270 A KR970024270 A KR 970024270A
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KR
South Korea
Prior art keywords
point metal
melting point
manufacturing
high melting
single crystal
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Application number
KR1019950037202A
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Korean (ko)
Inventor
장규환
권영민
이병진
고용선
Original Assignee
김광호
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 김광호, 삼성전자 주식회사 filed Critical 김광호
Priority to KR1019950037202A priority Critical patent/KR970024270A/en
Publication of KR970024270A publication Critical patent/KR970024270A/en

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Abstract

본 발명은 얇은 접합(shallow junction) 구조를 위하여 샐리사이드구조를 갖는 반도체장치의 제조방법이 개시되어 있다.The present invention discloses a method of manufacturing a semiconductor device having a salicide structure for a thin junction structure.

본 발명의 제조방법은, 폴리실리콘 게이트 측벽에 절연스페이서를 형성하는 공정, 선택적 에피택셜 성장(SEG) 공정을 이용하여 노출된 반도체기판상에 단결정 실리콘층을 성장시키는 공정, 상기 결과물의 전면에 고융점금속을 증착시키는 공정, 열적공정을 수행하여 상기 폴리실리콘층 및 단결정 실리콘층과 고융점 금속이 접촉하는 부분에 금속실리사이드층을 형성하는 공정, 및 미반응의 상기 고융점금속을 제거하는 공정을 포함하여 이루어진다.The manufacturing method of the present invention comprises the steps of forming an insulating spacer on the polysilicon gate sidewall, growing a single crystal silicon layer on the exposed semiconductor substrate using a selective epitaxial growth (SEG) process, A step of depositing a melting point metal, a step of forming a metal silicide layer at a portion where the polysilicon layer, the single crystal silicon layer and the high melting point metal contact by performing a thermal process, and removing the unreacted high melting point metal. It is made to include.

따라서, 별도의 패터닝공정을 하지않고 고용점금속층을 제거할 수 있기 때문에 공정의 단순화 효과가 있다.Therefore, since the solid solution point metal layer can be removed without a separate patterning process, the process is simplified.

Description

금속-샐리사이드 구조를 갖는 반도체장치의 제조방법Method for manufacturing a semiconductor device having a metal-salicide structure

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제2A도 내지 제2E도는 본 발명의 일 실시예에 의한 티타늄-샐리사이드 구조를 형성하는 과정을 나타내는 단면도들이다.2A through 2E are cross-sectional views illustrating a process of forming a titanium-salicide structure according to an embodiment of the present invention.

Claims (3)

필드산화막에 의해 한정되는 반도체기판의 소자활성영역내에 폴리실리콘 게이트구조를 형성한후 게이트 측벽에 절연스페이서를 형성하는 공정; 선택적 에피택셜 성장(SEG) 공정을 이용하여 상기 필드산화막과 절연스페이서 사이에서 노출된 반도체기판상에 단결정 실리콘층을 성장시키는 공정; 상기 견과물의 전면에 고융점금속을 증착시키는 공정 열적 공정을 수행하여 상기 폴리실리콘층 및 단결정 실리콘층과 고융점 금속이 접촉하는 부분에 금속실리사이드층을 형성하는 공정; 및 미반응의 상기 고융점금속을 제거하는 공정; 을 포함하여 이루어지는 것을 특징으로 하는 반도체장치의 제조방법.Forming a polysilicon gate structure in the device active region of the semiconductor substrate defined by the field oxide film and then forming an insulating spacer on the gate sidewall; Growing a single crystal silicon layer on the exposed semiconductor substrate between the field oxide film and the insulating spacer using a selective epitaxial growth (SEG) process; Depositing a high melting point metal on the entire surface of the nut to form a metal silicide layer on a portion where the polysilicon layer, the single crystal silicon layer and the high melting point metal are in contact with each other; And removing the unreacted high melting point metal. A manufacturing method of a semiconductor device comprising a. 제 1항에 있어서, 상기 고융점금속은 티타늄인 것을 특징으로 하는 상기 반도체장치의 제조방법.The method of claim 1, wherein the high melting point metal is titanium. 제 2항에 있어서, 상기 SEG 공정에 의해 성장되는 단결정 실리콘층은 100Å 이하가 되도록 형성하는 것을 특징으로 하는 상기 반도체장치의 제조방법.The method of manufacturing the semiconductor device according to claim 2, wherein the single crystal silicon layer grown by the SEG process is formed to be 100 kHz or less. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950037202A 1995-10-25 1995-10-25 Method for manufacturing a semiconductor device having a metal-salicide structure KR970024270A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950037202A KR970024270A (en) 1995-10-25 1995-10-25 Method for manufacturing a semiconductor device having a metal-salicide structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950037202A KR970024270A (en) 1995-10-25 1995-10-25 Method for manufacturing a semiconductor device having a metal-salicide structure

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KR970024270A true KR970024270A (en) 1997-05-30

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR19990000867A (en) * 1997-06-11 1999-01-15 윤종용 Salicide structure of semiconductor device and manufacturing method thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR19990000867A (en) * 1997-06-11 1999-01-15 윤종용 Salicide structure of semiconductor device and manufacturing method thereof

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