KR970023980A - PBL device isolation method for semiconductor devices - Google Patents

PBL device isolation method for semiconductor devices Download PDF

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Publication number
KR970023980A
KR970023980A KR1019950034567A KR19950034567A KR970023980A KR 970023980 A KR970023980 A KR 970023980A KR 1019950034567 A KR1019950034567 A KR 1019950034567A KR 19950034567 A KR19950034567 A KR 19950034567A KR 970023980 A KR970023980 A KR 970023980A
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KR
South Korea
Prior art keywords
film
pbl
polysilicon film
device isolation
isolation method
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Application number
KR1019950034567A
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Korean (ko)
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KR100189974B1 (en
Inventor
김영선
김영대
Original Assignee
김광호
삼성전자 주식회사
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Priority to KR1019950034567A priority Critical patent/KR100189974B1/en
Publication of KR970023980A publication Critical patent/KR970023980A/en
Application granted granted Critical
Publication of KR100189974B1 publication Critical patent/KR100189974B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Local Oxidation Of Silicon (AREA)
  • Element Separation (AREA)

Abstract

필드산화막에 발생하는 2차 버즈빅(Second Bird's Beak)을 제거할 수 있는 PBL 소자분리 방법이 포함되어 있다.PBL device isolation is included to eliminate secondary birds' beaks in field oxide films.

본 발명은 폴리실리콘막의 전면에 질화막(SiN)을 적층시키기 전에 상기 폴리실리콘막의 표면에 잔류하는 네이티브 옥사이드(Native Oxide)를 완전히 제거함으로써, 종래의 PBL 소자분리 방법에서 발생되는 2차 버즈빅을 방지할 수 있고, 또한 LOCOS 소자분리 방법에 비해 버즈빅의 길이를 줄일 수 있다.The present invention completely removes the native oxide remaining on the surface of the polysilicon film before stacking the nitride film (SiN) on the entire surface of the polysilicon film, thereby preventing secondary buzz big generated in the conventional PBL device isolation method. In addition, it can reduce the length of the Buzzvik compared to the LOCOS isolation method.

Description

반도체장치의 PBL 소자분리 방법PBL device isolation method for semiconductor devices

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제5도 내지 제9도는 본 발명의 실시예에 의한 PBL 소자분리 방법을 나타내는 도면이다.5 to 9 are diagrams illustrating a PBL device isolation method according to an embodiment of the present invention.

Claims (3)

반도체장치의 PBL 소자분리 방법에 있어서, 실리콘기판의 전면에 패드산화막(Pad Oxide), 폴리실리콘막을 순차적으로 적층하는 단계; 상기 폴리실리콘막 위에 잔류하는 네이티브 옥사이드(Native Oxide)를 제거하는 단계; 상기 결과물의 전면에, 대기중에 노출되지 않은 상태에서 질화막(SiN)을 적층하는 단계, 상기 질화막중에서 필드영역이 형성될 부분을 제거하고 질화막패턴을 형성하는 단계; 상기 결과물의 전면에 열산화 공정에 의해 필드산화막을 형성하는 단계; 상기 질화막패턴과 상기 폴리실리콘막, 및 상기 패드산화막을 제거하는 단계를 순차적으로 수행하는 것을 특징으로 하는 반도체장치의 PBL 소자분리 방법.A PBL device isolation method for a semiconductor device, the method comprising: sequentially depositing a pad oxide film and a polysilicon film on a front surface of a silicon substrate; Removing native oxide remaining on the polysilicon film; Stacking a nitride film (SiN) on the entire surface of the resultant in a state of not being exposed to the air, removing a portion of the nitride film on which a field region is to be formed, and forming a nitride film pattern; Forming a field oxide film on the entire surface of the result by a thermal oxidation process; And sequentially removing the nitride film pattern, the polysilicon film, and the pad oxide film. 제1항에 있어서, 상기 폴리실리콘막의 표면에 잔류하는 상기 네이티브 옥사이드(Native Oxide)를 제거하는 방법으로서 800℃ 이상의 온도에서 H2가스를 이용하는 것을 특징으로 하는 반도체장치의 PBL 소자분리 방법.The method of claim 1, wherein H 2 gas is used at a temperature of 800 ° C. or higher as a method of removing the native oxide remaining on the surface of the polysilicon film. 제1항에 있어서, 상기 폴리실리콘막의 표면에 잔류하는 상기 네이티브 옥사이드(Native Oxide)를 제거하는 방법으로서 건식식각 및 습식식각중의 한가지 방법을 이용하는 것을 특징으로 하는 반도체장치의 PBL 소자분리 방법.2. The method of claim 1, wherein one of dry etching and wet etching is used as a method of removing the native oxide remaining on the surface of the polysilicon film. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950034567A 1995-10-09 1995-10-09 Method for forming a pbl element isolation region in a semiconductor device KR100189974B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950034567A KR100189974B1 (en) 1995-10-09 1995-10-09 Method for forming a pbl element isolation region in a semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950034567A KR100189974B1 (en) 1995-10-09 1995-10-09 Method for forming a pbl element isolation region in a semiconductor device

Publications (2)

Publication Number Publication Date
KR970023980A true KR970023980A (en) 1997-05-30
KR100189974B1 KR100189974B1 (en) 1999-06-01

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KR1019950034567A KR100189974B1 (en) 1995-10-09 1995-10-09 Method for forming a pbl element isolation region in a semiconductor device

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KR100189974B1 (en) 1999-06-01

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