KR970023407A - High speed I / O driver structure - Google Patents

High speed I / O driver structure Download PDF

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Publication number
KR970023407A
KR970023407A KR1019950034953A KR19950034953A KR970023407A KR 970023407 A KR970023407 A KR 970023407A KR 1019950034953 A KR1019950034953 A KR 1019950034953A KR 19950034953 A KR19950034953 A KR 19950034953A KR 970023407 A KR970023407 A KR 970023407A
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KR
South Korea
Prior art keywords
output
pull
gate
dou1
pmos transistor
Prior art date
Application number
KR1019950034953A
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Korean (ko)
Inventor
안기식
신인철
Original Assignee
김광호
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 김광호, 삼성전자 주식회사 filed Critical 김광호
Priority to KR1019950034953A priority Critical patent/KR970023407A/en
Publication of KR970023407A publication Critical patent/KR970023407A/en

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  • Logic Circuits (AREA)

Abstract

본 발명은 풀업 및 풀 다운 수단을 구비하여 고속용 입출력 드라이버의 구조에 관한 것으로서, 풀업용으로 사용되는 바이폴라 트랜지스터, 제1PMOS트랜지스터 및 제2PMOS트랜지스터; 풀다운용으로 사용되는 제1NMOS트랜지스터 및 제2NMOS트랜지스터; 입력신호 DOU1, HVDO1, DOU1과 위상이 반대이면서 일정시간 지연된 신호를 만드는 지연블럭; 상기 지연블럭의 출력을 받아들이는 NOR게이트; 상기 상기 NOR게이트의 출력이 상기 풀다운용 제2NMOS트랜지스터의 게이트에 연결되며, 상기 지연 블럭의 출력을 받아들이는 NAND게이트; 및 상기 NAND게이트의 출력이 상기 제2PMOS트랜지스터에 연결되고 상기 DOU1신호를 받아들이는 인버터의 출력이 상기 제1PMOS트랜지스터의 게이트에 연결된 구조를 갖는다.The present invention relates to a structure of a high speed input / output driver having a pull-up and pull-down means, comprising: a bipolar transistor, a first PMOS transistor, and a second PMOS transistor used for a pull-up; A first NMOS transistor and a second NMOS transistor used for pull-down; A delay block for generating a signal delayed for a predetermined time while being in phase with the input signals DOU1, HVDO1, and DOU1; A NOR gate receiving the output of the delay block; A NAND gate connected to an output of the NOR gate to a gate of the second NMOS transistor for pull-down, and receiving an output of the delay block; And an output of the NAND gate is connected to the second PMOS transistor, and an output of the inverter receiving the DOU1 signal is connected to the gate of the first PMOS transistor.

따라서 상술한 바와 같이 본 발명에 따른 고속용 입출력 드라이버는 종래의 회로에 추가의 풀업 수단 및 풀다운 수단을 구비함으로써, 버퍼의 속도를 높이는 효과를 갖는다.Therefore, as described above, the high-speed input / output driver according to the present invention has an effect of increasing the speed of the buffer by providing additional pull-up means and pull-down means in the conventional circuit.

Description

고속용 입출력 드라이버 구조High speed I / O driver structure

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제2도는 본 발명에 따른 입출력 드라이버의 구조를 보이는 회로도이다.2 is a circuit diagram showing the structure of an input / output driver according to the present invention.

Claims (1)

입출력 드라이버 구조에 있어서, 풀업용으로 사용되는 바이폴라 트랜지스터, 제1PMOS트랜지스터 및 제2PMOS트랜지스터; 풀다운용으로 사용되는 제1NMOS트랜지스터 및 제2NMOS트랜지스터; 입력신호 DOU1, HVDO1, DOU1과 위상이 반대이면서 일정 시간 지연된 신호를 만드는 지연블럭; 상기 지연블럭의 출력(DOU1, HVDO2)을 받아들이는 NOR게이트; 상기 상기 NOR게이트의 출력이 상기 풀다운용 제2NMOS의 게이트에연결되며, 상기 지연 블럭의 출력을 받아들이는 NAND게이트; 및 상기 NAND게이트의 출력이 상기 제2PMOS트랜지스터에 연결되고 상기 DOU1신호를 받아들이는 인버터의 출력이 상기 제1PMOS트랜지스터의 게이트에 연결된 구조를 갖는 것을 특징으로 하는 고속입출력 드라이버 구조.An input / output driver structure comprising: a bipolar transistor, a first PMOS transistor, and a second PMOS transistor used for pull-up; A first NMOS transistor and a second NMOS transistor used for pull-down; A delay block for generating a signal delayed for a predetermined time out of phase with the input signals DOU1, HVDO1, and DOU1; A NOR gate receiving the outputs DOU1 and HVDO2 of the delay block; An NAND gate connected to an output of the NOR gate and connected to a gate of the second NMOS for pull-down, and receiving an output of the delay block; And an output of the NAND gate is connected to the second PMOS transistor, and an output of the inverter receiving the DOU1 signal is connected to a gate of the first PMOS transistor. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950034953A 1995-10-11 1995-10-11 High speed I / O driver structure KR970023407A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950034953A KR970023407A (en) 1995-10-11 1995-10-11 High speed I / O driver structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950034953A KR970023407A (en) 1995-10-11 1995-10-11 High speed I / O driver structure

Publications (1)

Publication Number Publication Date
KR970023407A true KR970023407A (en) 1997-05-30

Family

ID=66583719

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950034953A KR970023407A (en) 1995-10-11 1995-10-11 High speed I / O driver structure

Country Status (1)

Country Link
KR (1) KR970023407A (en)

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