KR970022346A - Semiconductor chip packaging inspection device and inspection method - Google Patents

Semiconductor chip packaging inspection device and inspection method Download PDF

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Publication number
KR970022346A
KR970022346A KR1019950036249A KR19950036249A KR970022346A KR 970022346 A KR970022346 A KR 970022346A KR 1019950036249 A KR1019950036249 A KR 1019950036249A KR 19950036249 A KR19950036249 A KR 19950036249A KR 970022346 A KR970022346 A KR 970022346A
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KR
South Korea
Prior art keywords
semiconductor chip
lead
applying
wire
chip
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KR1019950036249A
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Korean (ko)
Inventor
고금식
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김광호
삼성전자 주식회사
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Priority to KR1019950036249A priority Critical patent/KR970022346A/en
Publication of KR970022346A publication Critical patent/KR970022346A/en

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Abstract

본 발명은 개별 칩이 리드 프레임에 와이어에 의해서 연결되었을 시 새깅(sagging)된 부분을 사전에 검출하기 위해서 새깅 부위의 의도적인 단락을 일으킬 수 있는 바이어싱 조건을 부여하여 새깅을 검출하는 회로 및 그 수행 방법에 관한 것으로, 본 회로는 반도체 칩의 소정 부위와 리드 프레임의 리드에 와이어 본딩 접속된 구조체에서, 와이어와 칩과의 근접 위치 새깅을 검출하기 위해서 이 부위에서 의도적인 단락이 발생되는 것에 의해 불량 칩을 선별하도록 선택된 리드에 전기적 바이어스를 인가하기 위한 회로를 포함하며, 검사 방법은 바이어스 인가 후 단락 여부에 의해 불량 칩 선별하는 과정을 갖는다.The present invention provides a circuit for detecting sagging by giving a biasing condition that can cause an intentional short circuit of the sagging portion in order to detect a sagging portion in advance when an individual chip is connected by a wire to the lead frame. The present invention relates to a method of performing a circuit in which a structure is connected by wire bonding to a predetermined portion of a semiconductor chip and a lead of a lead frame, whereby an intentional short circuit occurs at this portion to detect a sagging position of the wire and the chip. And a circuit for applying an electrical bias to the lead selected to screen the bad chip, wherein the inspection method includes a process of screening the bad chip by short circuit after applying the bias.

Description

반도체 칩 패키징 검사 장치 및 검사 방법Semiconductor chip packaging inspection device and inspection method

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제1도는 개별 칩이 리드 프레임에 와이어에 의해서 연결되었을 시 새깅된 부분을 나타낸 단면으로 도시한 도면,1 is a cross-sectional view showing a portion sagged when the individual chip is connected by a wire to the lead frame,

제2도는 제1도의 구조체의 새깅 검출을 위한 반도체 칩 패키징 검사 장치에 대한 개략적인 회로도를 나타낸 도면.FIG. 2 is a schematic circuit diagram of a semiconductor chip packaging inspection apparatus for sagging detection of the structure of FIG.

Claims (4)

반도체 칩의 소정 부위와 리드를 갖는 리드 프레임의 상기 리드에 와이어 본딩 접속된 구조체에서, 상기 와이어와 상기 칩과의 근접 위치 새깅(sagging)을 검출하기 위해서 상기 부위에서 의도적인 단락이 발생되는 것에 의해 불량 칩을 선별하도록 상기 선택된 리드에 전기적 바이어스를 인가하기 위한 수단을 포함하는 것을 특징으로 하는 반도체 칩 패키징 검사 장치.In a structure wire-bonded to a lead of a lead frame having a lead and a predetermined portion of a semiconductor chip, an intentional short circuit occurs at the portion to detect sagging of the wire and the chip. And means for applying an electrical bias to the selected lead to screen out bad chips. 제1항에 있어서, 상기 반도체 칩은 콜렉터, 베이스 및 에미터를 갖는 바이폴라 트랜지스터이며, 상기 바이어스 인가 수단은 상기 베이스와 에미터 인출 리드를 단락시킨 상태에서 상기 콜렉터와 에이터간에 전류를 인가하는 수단인 것을 특징으로 하는 반도체 칩 패키징 검사 장치.The semiconductor chip according to claim 1, wherein the semiconductor chip is a bipolar transistor having a collector, a base, and an emitter, and the bias applying means is a means for applying a current between the collector and the actor while shorting the base and emitter lead. Semiconductor chip packaging inspection device, characterized in that. 반도체 칩의 소정 부위와 리드를 갖는 리드 프레임의 상기 리드에 와이어 본딩 접속하는 단계; 및 상기 와이어와 상기 칩과의 근접 위치 새깅을 검출하기 위해시 상기 선택된 리드에 전기척 바이어스를 인가하는 단계를 포함하며, 상기 새깅 부위에서 의도적인 단락이 발생되는 것에 의해 불량 칩을 선별하도록 한 것을 특징으로 하는 반도체 칩 패키징 검사 방법.Wire-bonding a predetermined portion of a semiconductor chip to the lead of the lead frame having the lead; And applying an electric chuck bias to the selected lead upon detecting a near position sagging of the wire and the chip, wherein the intentional short circuit occurs at the sagging site to select a defective chip. A semiconductor chip packaging inspection method. 제3항에 있어서, 상기 반도체 칩은 콜렉터, 베이스 및 에미터를 갖는 바이폴라 트랜지스터이며, 상기 바이어스 인가 수단은 상기 베이스와 에미터 인출 리드를 단락시킨 상태에서 상기 콜렉터와 에미터간에 전류를 인가하는 수단인 것을 특징으로 하는 반도체 칩 패키징 검사 방법.4. The semiconductor chip of claim 3, wherein the semiconductor chip is a bipolar transistor having a collector, a base, and an emitter, and the bias applying means is a means for applying a current between the collector and the emitter while the base and the emitter withdrawal lead are shorted. The semiconductor chip packaging inspection method characterized by the above-mentioned. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950036249A 1995-10-19 1995-10-19 Semiconductor chip packaging inspection device and inspection method KR970022346A (en)

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KR1019950036249A KR970022346A (en) 1995-10-19 1995-10-19 Semiconductor chip packaging inspection device and inspection method

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KR1019950036249A KR970022346A (en) 1995-10-19 1995-10-19 Semiconductor chip packaging inspection device and inspection method

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KR970022346A true KR970022346A (en) 1997-05-28

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20170128954A (en) 2016-05-16 2017-11-24 주식회사 마인즈아이 Apparatus for inspecting substrate

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20170128954A (en) 2016-05-16 2017-11-24 주식회사 마인즈아이 Apparatus for inspecting substrate

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