KR970022346A - Semiconductor chip packaging inspection device and inspection method - Google Patents
Semiconductor chip packaging inspection device and inspection method Download PDFInfo
- Publication number
- KR970022346A KR970022346A KR1019950036249A KR19950036249A KR970022346A KR 970022346 A KR970022346 A KR 970022346A KR 1019950036249 A KR1019950036249 A KR 1019950036249A KR 19950036249 A KR19950036249 A KR 19950036249A KR 970022346 A KR970022346 A KR 970022346A
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- semiconductor chip
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- wire
- chip
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- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Abstract
본 발명은 개별 칩이 리드 프레임에 와이어에 의해서 연결되었을 시 새깅(sagging)된 부분을 사전에 검출하기 위해서 새깅 부위의 의도적인 단락을 일으킬 수 있는 바이어싱 조건을 부여하여 새깅을 검출하는 회로 및 그 수행 방법에 관한 것으로, 본 회로는 반도체 칩의 소정 부위와 리드 프레임의 리드에 와이어 본딩 접속된 구조체에서, 와이어와 칩과의 근접 위치 새깅을 검출하기 위해서 이 부위에서 의도적인 단락이 발생되는 것에 의해 불량 칩을 선별하도록 선택된 리드에 전기적 바이어스를 인가하기 위한 회로를 포함하며, 검사 방법은 바이어스 인가 후 단락 여부에 의해 불량 칩 선별하는 과정을 갖는다.The present invention provides a circuit for detecting sagging by giving a biasing condition that can cause an intentional short circuit of the sagging portion in order to detect a sagging portion in advance when an individual chip is connected by a wire to the lead frame. The present invention relates to a method of performing a circuit in which a structure is connected by wire bonding to a predetermined portion of a semiconductor chip and a lead of a lead frame, whereby an intentional short circuit occurs at this portion to detect a sagging position of the wire and the chip. And a circuit for applying an electrical bias to the lead selected to screen the bad chip, wherein the inspection method includes a process of screening the bad chip by short circuit after applying the bias.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.
제1도는 개별 칩이 리드 프레임에 와이어에 의해서 연결되었을 시 새깅된 부분을 나타낸 단면으로 도시한 도면,1 is a cross-sectional view showing a portion sagged when the individual chip is connected by a wire to the lead frame,
제2도는 제1도의 구조체의 새깅 검출을 위한 반도체 칩 패키징 검사 장치에 대한 개략적인 회로도를 나타낸 도면.FIG. 2 is a schematic circuit diagram of a semiconductor chip packaging inspection apparatus for sagging detection of the structure of FIG.
Claims (4)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019950036249A KR970022346A (en) | 1995-10-19 | 1995-10-19 | Semiconductor chip packaging inspection device and inspection method |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019950036249A KR970022346A (en) | 1995-10-19 | 1995-10-19 | Semiconductor chip packaging inspection device and inspection method |
Publications (1)
Publication Number | Publication Date |
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KR970022346A true KR970022346A (en) | 1997-05-28 |
Family
ID=66584358
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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KR1019950036249A KR970022346A (en) | 1995-10-19 | 1995-10-19 | Semiconductor chip packaging inspection device and inspection method |
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KR (1) | KR970022346A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20170128954A (en) | 2016-05-16 | 2017-11-24 | 주식회사 마인즈아이 | Apparatus for inspecting substrate |
-
1995
- 1995-10-19 KR KR1019950036249A patent/KR970022346A/en not_active Application Discontinuation
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20170128954A (en) | 2016-05-16 | 2017-11-24 | 주식회사 마인즈아이 | Apparatus for inspecting substrate |
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