KR20020056291A - Test pattern of semiconductor device - Google Patents

Test pattern of semiconductor device Download PDF

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Publication number
KR20020056291A
KR20020056291A KR1020000085614A KR20000085614A KR20020056291A KR 20020056291 A KR20020056291 A KR 20020056291A KR 1020000085614 A KR1020000085614 A KR 1020000085614A KR 20000085614 A KR20000085614 A KR 20000085614A KR 20020056291 A KR20020056291 A KR 20020056291A
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KR
South Korea
Prior art keywords
gate electrode
semiconductor device
transistor
test pattern
source electrode
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KR1020000085614A
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Korean (ko)
Inventor
김헌준
김진하
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박종섭
주식회사 하이닉스반도체
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Priority to KR1020000085614A priority Critical patent/KR20020056291A/en
Publication of KR20020056291A publication Critical patent/KR20020056291A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H01L22/34—Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors

Abstract

PURPOSE: A test pattern of a semiconductor device is provided to easily detect a junction defect of tungsten and polysilicon, by determining whether the voltage applied to the tungsten formed on a gate electrode is transmitted to the polysilicon formed under the gate electrode. CONSTITUTION: A plurality of n-channel metal oxide semiconductor(NMOS) transistors having a stack structure of a polysilicon layer and a tungsten layer are interconnected in series. An input terminal is coupled to a gate electrode of the first transistor. Plus voltage is applied to respective drain electrodes. A source electrode is coupled to a gate electrode at an output terminal. A source electrode of the final transistor is coupled to the output terminal.

Description

반도체소자의 테스트패턴{TEST PATTERN OF SEMICONDUCTOR DEVICE}TEST PATTERN OF SEMICONDUCTOR DEVICE

본 발명은 반도체소자의 테스트패턴에 관한 것으로서, 특히 반도체소자의 고집적화에 따라 트랜지스터의 저항이 증가하면서 금속층을 사용하여 게이트전극을 형성할 때 유발되는 금속층과 폴리실리콘과의 접합(adhesion)을 테스트하는 기술에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a test pattern of a semiconductor device, and more particularly, to test an adhesion between a metal layer and polysilicon caused when a gate electrode is formed using a metal layer while the resistance of the transistor increases with increasing integration of the semiconductor device. It's about technology.

현재, 폴리실리콘과 금속층 적층구조의 게이트전극은 명확한 테스트 패턴이없다.At present, the gate electrode of the polysilicon and metal layer stack structure does not have a clear test pattern.

이로인하여, 공정조건을 찾기 위하여 접합 불량 지역을 찾아 해당지역의 단면을 분석하는 방법만을 사용하고 있다.Therefore, in order to find the process conditions, only the method of finding the defective joint area and analyzing the cross section of the corresponding area is used.

그러나, 이런 방법은 대부분의 시간을 접합 불량 지역을 검출하는데 사용하게 되어 효율성을 저하시킨다.However, this method spends most of the time detecting dead areas, which reduces efficiency.

그리고, 평면도를 관찰하는 방법으로 불량 지역을 찾기 때문에 해당지역을 찾기가 어려운 문제점이 있다.In addition, there is a problem in that it is difficult to find a corresponding area because the defective area is found by observing the plan view.

본 발명은 상기 종래의 문제점을 해소하기 위하여 안출한 것으로서, 텅스텐과 폴리실리콘의 접합 불량 부분을 용이하게 검출할 수 있는 테스트 패턴을 제공하여 반도체소자의 생산성 및 수율을 향상시키는 반도체소자의 테스트패턴을 제공함에 그 목적이 있다.The present invention has been made in order to solve the above-mentioned problems, and provides a test pattern that can easily detect the defective bonding portion of tungsten and polysilicon to improve the productivity and yield of the semiconductor device test pattern The purpose is to provide.

도 1 및 도 2는 본 발명에 제1실시예에 따른 반도체소자의 테스트패턴을 도시한 회로도와 레이아웃도.1 and 2 are a circuit diagram and a layout diagram showing a test pattern of a semiconductor device according to a first embodiment of the present invention.

도 3은 본 발명에 제2실시예에 따른 반도체소자의 테스트패턴을 도시한 회로도.3 is a circuit diagram showing a test pattern of a semiconductor device according to a second embodiment of the present invention.

<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>

100 : 활성영역 200 : 게이트전극100: active region 200: gate electrode

300 : 제1금속배선 400 : 제1금속배선과 활성영역의 콘택부300: first metal wiring 400: contact portion of the first metal wiring and the active region

500 : 제1금속배선과 게이트전극의 콘택부500: contact portion of the first metal wiring and the gate electrode

상기 목적을 달성하기 위한 본 발명에 따른 반도체소자의 테스트패턴은, 폴리실리콘막과 텅스텐막의 적층구조로 구비되는 다수의 엔/피 모스 트랜지스터가 직렬로 연결되되, 입력단이 접속되는 최초 트랜지스터의 게이트전극, 플러스/마이너스의 전압이 인가되는 각각의 드레인전극, 출력단 측의 게이트전극에 접속된 소오스전극이 구비되고, 최후 트랜지스터의 소오스전극이 출력단에 접속된 것을 특징으로 한다.In the test pattern of the semiconductor device according to the present invention for achieving the above object, the gate electrode of the first transistor that is connected in series with a plurality of N / PMOS transistor provided in a laminated structure of a polysilicon film and a tungsten film, the input terminal is connected And a drain electrode connected to each of the drain electrodes to which a positive / negative voltage is applied, and a gate electrode on the output terminal side, and a source electrode of the last transistor is connected to the output terminal.

한편, 본 발명의 원리는 다음과 같다.On the other hand, the principle of the present invention is as follows.

게이트전극을 형성하는 텅스텐과 폴리실리콘의 접합 불량을 검출하기 위하여 텅스텐에 전압을 인가하여 폴리실리콘에 전달되는가를 확인하는 것으로서, 상기 폴리실리콘에 전압이 전달되지 않는 경우는 트랜지스터의 채널 영역의 인버전(inversion) 이 유도되지 않는 현상을 이용하는 것이다.In order to detect a failure in bonding the tungsten and the polysilicon forming the gate electrode, a voltage is applied to the tungsten to determine whether it is transferred to the polysilicon. When no voltage is transferred to the polysilicon, the inversion of the channel region of the transistor is performed. This is to use the phenomenon that inversion is not induced.

여기서, 트랜지스터가 턴온(turn on) 되지 않으면 다양한 오픈 페일(open fail) 현상이 발생된다. 따라서, 다수의 단위 트랜지스터를 직렬 배열하면 채널 지역의 인버전이 유도되지않는 경우가 검출될 수 있어 해당 공정 스플릿(split)의 여러 결과를 페일 포인트(fail point)의 검출 없이 전기적 검사로 알 수 있다.Here, various open fail phenomena occur when the transistor is not turned on. Accordingly, when a plurality of unit transistors are arranged in series, a case in which inversion of a channel region is not induced may be detected, and various results of the corresponding process split may be detected by an electrical test without detecting a fail point. .

이하, 첨부된 도면을 참고로 하여 본 발명을 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

도 1 내지 도 3 은 본 발명의 실시예에 따른 반도체소자의 테스트패턴을 도시한 회로도 및 레이아웃도이다.1 to 3 are circuit diagrams and layouts showing test patterns of a semiconductor device according to an embodiment of the present invention.

도 1 및 도 2 는 본 발명에 따라 엔모스(NMOS)의 경우를 도시한 회로도 및 레이아웃도이다.1 and 2 are circuit diagrams and layout diagrams illustrating a case of NMOS according to the present invention.

도 1를 참조하면, 다수의 엔모스 트랜지스터가 직렬로 연결되되, 입력단이 접속되는 최초 트랜지스터의 게이트전극, 플러스의 전압이 인가되는 각각의 드레인전극, 출력단 측의 게이트전극에 접속된 소오스전극이 구비되고, 최후 트랜지스터의 소오스전극이 출력단에 접속된 것이다.Referring to FIG. 1, a plurality of NMOS transistors are connected in series and include a gate electrode of an initial transistor to which an input terminal is connected, a drain electrode to which a positive voltage is applied, and a source electrode connected to a gate electrode of an output terminal side. The source electrode of the last transistor is connected to the output terminal.

이때, 게이트전극의 턴온 전압을 병렬연결하게 되므로 단위 트랜지스터의 숫자는 웰 픽업(well pick-up)의 마진이 허락하는 한 무한대로 배열하여 테스트 할 수 있으며, 게이트전극의 크기를 최소화하고 타 불량 가능성을 최소화 함으로써 순수한 게이트전극 구조 평가용으로 사용될 수 있다. 또한, 에미션(emition)장비를 이용하면 트랜지스터의 직렬 배열에서 전류가 끊어지는 부분을 명확하게 알 수 있어 불량지역을 용이하게 검출할 수 있다.At this time, since the turn-on voltage of the gate electrode is connected in parallel, the number of unit transistors can be tested by arranging them indefinitely as the margin of the well pick-up allows, minimizing the size of the gate electrode and possibly other defects. By minimizing this, it can be used for the evaluation of pure gate electrode structure. In addition, the use of the emission equipment makes it possible to clearly identify the portion of the transistor in which the current is cut off so that the defective area can be easily detected.

여기서, 테스트패턴의 동작시 불량 지점 이후의 트랜지스터는 플로팅(floating) 상태가 되며 이로인하여 출력단의 전류는 트랜지스터의 정상 턴온 상태과 많이 차이를 갖게 되며 게이트전극의 정상 유무를 판단할 수 있게 한다.Here, during operation of the test pattern, the transistor after the bad point is in a floating state, whereby the current of the output terminal is greatly different from the normal turn-on state of the transistor, and it is possible to determine whether the gate electrode is normal.

도 2를 참조하면, 소오스 전극 단이 출력단 측 트랜지스터의 게이트전극에 접속되어 게이트전극의 식각공정 발생되는 안테나 효과(antenna effecr)를 방지한다.Referring to FIG. 2, the source electrode terminal is connected to the gate electrode of the transistor on the output side to prevent an antenna effect generated during the etching process of the gate electrode.

여기서, 100 은 활성영역, 200 은 게이트전극, 300 은 제1금속배선을 도시하며, 400 은 상기 제1금속배선(300)이 상기 활성영역(100)에 콘택된 부분을 도시하고, 500 은 상기 제1금속배선(300)이 상기 게이트전극(200)에 콘택된 부분을 도시한다.Here, 100 is an active region, 200 is a gate electrode, 300 is a first metal wiring, 400 is a portion where the first metal wiring 300 is in contact with the active region 100, 500 is the A portion of the first metal wire 300 contacted with the gate electrode 200 is illustrated.

도 3 은 본 발명의 제2실시예에 따른 반도체소자의 테스트패턴을 도시한 회로도이다.3 is a circuit diagram illustrating a test pattern of a semiconductor device according to a second exemplary embodiment of the present invention.

도 3을 참조하면, 다수의 피모스 트랜지스터가 직렬로 연결되되, 입력단이 접속되는 최초 트랜지스터의 게이트전극, 마이너스의 전압이 인가되는 각각의 드레인전극, 출력단 측의 게이트전극에 접속된 소오스전극이 구비되고, 최후 트랜지스터의 소오스전극이 출력단에 접속된 것이다.Referring to FIG. 3, a plurality of PMOS transistors are connected in series and include a gate electrode of an initial transistor to which an input terminal is connected, a drain electrode to which a negative voltage is applied, and a source electrode connected to a gate electrode of an output terminal side. The source electrode of the last transistor is connected to the output terminal.

상기 도 3에 따른 테스트 패턴의 동작은 상기 도 1의 테스트 패턴과 동일한방식으로 불량을 검출할 수 있다.The operation of the test pattern according to FIG. 3 may detect a defect in the same manner as the test pattern of FIG. 1.

이상에서 설명한 바와 같이 본 발명에 따른 반도체소자의 테스트패턴은, 게이트전극의 상측에 구성되는 텅스텐에 가해진 전압이 상기 게이트전극의 하측에 구성되는 폴리실리콘에 전달되는지 여부를 판단하여 텅스텐과 폴리실리콘의 접합 불량을 용이하게 검출하여 반도체소자의 특성 및 수율을 향상시키는 효과를 제공한다.As described above, the test pattern of the semiconductor device according to the present invention determines whether the voltage applied to the tungsten formed on the upper side of the gate electrode is transmitted to the polysilicon formed on the lower side of the gate electrode. The defects can be easily detected to provide the effect of improving the characteristics and yield of the semiconductor device.

Claims (6)

폴리실리콘막과 텅스텐막의 적층구조로 구비되는 다수의 엔모스 트랜지스터가 직렬로 연결되되, 입력단이 접속되는 최초 트랜지스터의 게이트전극, 플러스의 전압이 인가되는 각각의 드레인전극, 출력단 측의 게이트전극에 접속된 소오스전극이 구비되고, 최후 트랜지스터의 소오스전극이 출력단에 접속된 것을 특징으로하는 반도체소자의 테스트패턴.A plurality of NMOS transistors in a stacked structure of a polysilicon film and a tungsten film are connected in series, connected to the gate electrode of the first transistor to which the input terminal is connected, to each drain electrode to which a positive voltage is applied, and to the gate electrode of the output terminal side. And a source electrode of the last transistor, wherein the source electrode of the last transistor is connected to the output terminal. 제 1 항에 있어서,The method of claim 1, 상기 다수의 엔모스 트랜지스터는 반도체소자의 웰 픽업 마진(well pick-up margin)에 따라 단위 트랜지스터의 숫자가 한정되는 것을 특징으로하는 반도체소자의 테스트 패턴.The plurality of NMOS transistors are a test pattern of a semiconductor device, characterized in that the number of unit transistors are limited according to the well pick-up margin of the semiconductor device. 제 1 항에 있어서,The method of claim 1, 상기 소오스 전극은 게이트전극의 클램프 다이오드(clamp diode)로 사용되는 것을 특징으로하는 반도체소자의 테스트 패턴.The source electrode is a test pattern of a semiconductor device, characterized in that used as a clamp diode of the gate electrode. 폴리실리콘막과 텅스텐막의 적층구조로 구비되는 다수의 피모스 트랜지스터가 직렬로 연결되되, 입력단이 접속되는 최초 트랜지스터의 게이트전극, 마이너스의 전압이 인가되는 각각의 드레인전극, 출력단 측의 게이트전극에 접속된 소오스전극이 구비되고, 최후 트랜지스터의 소오스전극이 출력단에 접속된 것을 특징으로하는 반도체소자의 테스트패턴.A plurality of PMOS transistors having a stacked structure of a polysilicon film and a tungsten film are connected in series, connected to the gate electrode of the first transistor to which the input terminal is connected, to each drain electrode to which a negative voltage is applied, and to the gate electrode on the output terminal side. And a source electrode of the last transistor, wherein the source electrode of the last transistor is connected to the output terminal. 제 4 항에 있어서,The method of claim 4, wherein 상기 다수의 피모스 트랜지스터는 반도체소자의 웰 픽업 마진(well pick-up margin)에 따라 단위 트랜지스터의 숫자가 한정되는 것을 특징으로하는 반도체소자의 테스트 패턴.The plurality of PMOS transistors are a test pattern of a semiconductor device, characterized in that the number of the unit transistor is limited according to the well pick-up margin (well pick-up margin) of the semiconductor device. 제 4 항에 있어서,The method of claim 4, wherein 상기 소오스 전극은 게이트전극의 클램프 다이오드(clamp diode)로 사용되는 것을 특징으로하는 반도체소자의 테스트 패턴.The source electrode is a test pattern of a semiconductor device, characterized in that used as a clamp diode of the gate electrode.
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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7436198B2 (en) 2004-01-20 2008-10-14 Samsung Electronics Co., Ltd. Test pattern of semiconductor device and test method using the same
KR100949884B1 (en) * 2007-10-29 2010-03-25 주식회사 하이닉스반도체 Test pattern
US9496192B2 (en) 2013-12-09 2016-11-15 Samsung Electronics Co., Ltd. Test pattern of semiconductor device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7436198B2 (en) 2004-01-20 2008-10-14 Samsung Electronics Co., Ltd. Test pattern of semiconductor device and test method using the same
KR100949884B1 (en) * 2007-10-29 2010-03-25 주식회사 하이닉스반도체 Test pattern
US9496192B2 (en) 2013-12-09 2016-11-15 Samsung Electronics Co., Ltd. Test pattern of semiconductor device

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