JPH047851A - Semiconductor device - Google Patents

Abstract

PURPOSE:To shorten the time for executing electric selection by arranging conductive metal on the surface of an open detection dummy viahole whose aperture size is equal to or smaller than a viahole, and checking electric continuity of the dummy viahole. CONSTITUTION:Open detection dummy viaholes 11 whose aperture sizes are equal to or smaller than a viahole, prove pads 12, and prove pins 13 are arranged outside source electrodes 1, and a bias voltage is applied from the probe pins 13, thereby detecting open failures of the following; the probe pad 12, conductive metal formed on the surface of the open detection dummy viahole 11, and a conducting route grounded to a stage 6 of a prober via a rear electrode 4. Since the aperture size of the dummy viahole 11 is equal to or smaller than the viahole for grounding the source electrodes 1, the depth is generally made shallow. In this manner, before electric selection of a chip 19 is performed, open detection of the viahole for grounding the source electrode 1 is performed, and the chip of open failure is selected, thereby reducing the time for executing electric selection.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a structure of a semiconductor device that can determine whether or not there is electrical continuity in a via hole portion of a semiconductor device provided with a via hole.

[Conventional technology]

Figure 5 shows C; aAsFET with conventional via holes.
6 is a top view showing the state of wafer probing.
A sectional view taken along line VI-Vl in the figure is shown.

In the figure, 1 is a source electrode having a via hole structure, 2 is a drain electrode, 3 is a gate electrode, 4 is a back electrode electrically connected to the source electrode 1 via a via hole penetrating the semiconductor substrate 5, and 6 is a back electrode. The stage 7 of the wafer prober indicates a probe needle of the wafer prober.

The wafer 8 that has undergone the front and back surface processing steps is subjected to electrical sorting for each chip 9. The wafer 8 placed on the stage 6 is normally electrically connected to the back electrode 4 of the wafer and grounded.

On the other hand, the drain electrode 2 and gate electrode 3 on the wafer surface
A bias is applied to each by the probe needle 7. The source electrode 1 is electrically connected to the back electrode 4 of the wafer through a by-hole, and is therefore grounded through the stage 6. Bias during electrical selection is positive for drain electrode 2, negative for gate electrode 3, and grounded for source electrode 1. The selection items are drain electrode 2 and source electrode 1.
The current between the gate electrode 3, the leakage current of the gate electrode 3, and the interruption of the drain-source current due to the bias of the gate electrode 3 are defined.

[Problem to be solved by the invention]

Since the grounding of each source electrode 1 of a conventional GaAsFET chip 9 is connected to the stage 6 via a via hole and the wafer back electrode 4, if all the source electrodes 1 are not electrically connected to the wafer back electrode 4. That is, when the source electrode 1 is open as shown in FIG.
Since no current flows between the source and drain, it can be determined that the product is defective.

However, if the number of island-shaped source electrodes is, for example, 50
In the case of a FET consisting of two FETs, even if one of them is an open defective product, the source-drain current will only decrease by about 1150 = 0.02 (2%), so the current distribution of normal crystals will vary. This makes it impossible to determine that the product is defective.

As described above, in the conventional structure, only an open defect in the source electrode 1 that deviates significantly from the current distribution of a normal crystal is detected, and an open defect within the current distribution is determined to be an acceptable product. This was causing temperature distribution fluctuations and deterioration and deterioration of characteristics.

The present invention has been made to solve the above-mentioned problems, and can detect open defects in multiple island-shaped source electrodes, determine them as defective products, and improve the uniformity of characteristics. The purpose is to obtain a semiconductor device.

[Means for Solving the Problems] The semiconductor device according to the present invention has a via hole that satisfies the main function possessed within the device or an opening formed separately in the chip whose size is equal to or smaller than the size of the via hole. A conductive metal is provided on the surface of the dummy via hole,
This is electrically connected to a probe pad formed on the front surface of the chip, and open defects in these via holes are detected through the probe pad.

[Effect]

Since the opening size of the dummy via hole for open detection in the present invention is set to be equal to or smaller than the via hole that satisfies the main function of the semiconductor device, the depth of the via hole is generally formed shallow. Therefore, if the dummy via hole is connected to the back electrode as a result of detecting an open defect in the dummy via hole through the probe pad, it is considered that the main via hole is securely connected, and the opening size is the same or smaller. If so, the contact area with the back electrode will be the same or less, and the contact condition with the back electrode, that is, the contact resistance, etc. will be in a more severe situation than with the main via hole. This can be reflected in the state of electrical contact with the via hole. Also,
When the open state of the main via hole itself is detected, the connection state between the via hole and the back electrode can be directly detected.

〔Example〕

Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a diagram showing a semiconductor device having a dummy via hole for open detection according to an embodiment of the semiconductor device of the present invention, and FIG. 2 is a diagram showing a cross-sectional structure taken along the line ■-■ in FIG. be. In the figure, the same symbols as in the conventional example indicate the same parts, and 11 is a dummy via hole for open detection, the surface of which is provided with conductive metal. 12 is a probe pad for open detection, 13 is a probe needle for open detection,
18 is a wafer, and 19 is a chip.

As shown in FIGS. 1 and 2, the structure of this embodiment consists of a dummy via hole 11 for open detection with an opening size equal to or smaller than that of the conventional FET, and a probe pad on the outside of the S-Sumi pole 1. I2 and probe needle 13 are added.

The wafer 18 that has undergone the front and back surface processing steps is subjected to electrical sorting for each chip 19.

The main electrical selection and selection items for GaAsFETs are the same as in the conventional example. However, in this embodiment, before selecting the main GaAsFET, open defects in the via hole for grounding the source electrode 1 are screened.

That is, a positive or negative bias is applied from the probe needle 13 and grounded to the stage 6 of the blow μ via the probe pad 12, the conductive metal provided on the surface of the open detection dummy via hole 11, and the back electrode 4. Detects open defects in conduction paths.

After this, the chips 9 that are not open defective are electrically selected.

In this embodiment, since the opening size of the open detection dummy via hole 11 is equal to or smaller than the via hole for grounding the source electrode 1, the depth of the via hole is generally formed shallow. Therefore, as a result of detecting an open defect in the dummy via hole 11 for open detection through the probe pad 2, if the dummy via hole 11 is connected to the back electrode 4, the via hole for grounding the source electrode 1 is surely connected. It is thought that the

In addition, if the opening size of the open detection dummy via hole 11 is equal to or smaller than the via hole for grounding the source electrode 1, the contact area with the back electrode will be the same or smaller, and the contact area between the open detection via hole 11 and the back electrode will be the same or smaller. The contact condition, ie, contact resistance, etc., will also be in a more severe situation than in the via hole for grounding the source electrode. Therefore, by detecting the contact resistance between the open detection dummy via hole 11 and the back electrode 4, it is possible to estimate the electrical contact state between the back electrode and the via hole for grounding the source electrode 1.

Furthermore, before performing electrical selection of the chip 19 in this way, open detection of the via hole for grounding the source electrode 1 is performed, and those with open defects are selected, thereby performing electrical selection. You can reduce the amount of time you spend doing this.

In addition, these open detection dummy via holes 11
Since they are arranged at the four corners of the chip 19, the same effect can be expected for each, and furthermore, each open detection via hole 11 is located at a distance from the via hole for grounding the source electrode 1 constituting the FET. Since it is far away, it can also be used to guarantee the thickness distribution of the semiconductor substrate 5 within the chip 19.

In the above embodiment, a dummy via hole 11 is provided in the chip 19, an open defect in the dummy via hole is detected by an open detection probe pad, and based on this result, it is determined whether or not the main via hole has an open defect. However, since the integration degree of the FET is low, the probe pad 12 for open detection is directly connected to the source electrode 1.
If it is possible to draw out the probe pad 12, which is electrically connected to the source electrode 1, only the probe pad 12 may be provided on the surface of the chip, and an open failure of the via hole for grounding the source electrode 1 may be directly detected.

That is, FIG. 3 shows a case where an open defect is detected using a via hole for grounding the source electrode l, and FIG. 4 shows a cross-sectional structure taken along the line IV--IV. In the figure,
The same reference numerals as in the conventional example indicate the same or corresponding parts, and in this embodiment, an open detection probe pad electrically connected to the grounding via hole of the source electrode 1 is provided on the surface of the substrate 5. , before electrically selecting the chip 19, the source electrode l is connected through the probe pad 12.
The purpose is to detect an open failure in the grounding via hole, determine whether the grounding via hole for source electrode 1 is securely connected, and select it. Naturally, this embodiment is similar to the above embodiment. A similar effect can be obtained.

〔Effect of the invention〕

In this invention, a conductive metal is provided on the surface of a via hole that fulfills the main function in the device or a dummy via hole for open detection whose opening size is equal to or smaller than the size of the via hole separately provided in the chip. This is connected to a probe pad that is electrically connected to the front surface of the chip, and an open defect in a via hole or dummy via hole is detected through the probe pad. Open defects in the main via holes can be detected or estimated, the time required for electrical selection can be shortened, and the uniformity of device characteristics can be improved.

[Brief explanation of drawings]

FIG. 1 shows an FE equipped with a via hole for open detection in a semiconductor device according to an embodiment of the present invention. In the figure, the same reference numerals indicate the same or corresponding parts.

Claims (1)

[Claims] (1) In a semiconductor device equipped with a via hole for electrically connecting the front side electrode and the back side electrode of the substrate, a device with an equivalent or smaller size provided on the surface of the via hole or on the outside of the via hole A conductive metal film provided on the surface of a dummy via hole having the size of an opening, and a probe pad formed on the surface side of the substrate to be electrically connected to the conductive metal film, and the via hole is connected to the via hole through the probe pad. A semiconductor device characterized in that a conduction check of the hole or the dummy via hole is performed.