JPS61237438A - Inspection of bonding - Google Patents
Inspection of bondingInfo
- Publication number
- JPS61237438A JPS61237438A JP60079956A JP7995685A JPS61237438A JP S61237438 A JPS61237438 A JP S61237438A JP 60079956 A JP60079956 A JP 60079956A JP 7995685 A JP7995685 A JP 7995685A JP S61237438 A JPS61237438 A JP S61237438A
- Authority
- JP
- Japan
- Prior art keywords
- bonding
- frequency current
- inspection method
- waveform
- adder
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
- H01L24/78—Apparatus for connecting with wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
- H01L2224/78—Apparatus for connecting with wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
- H01L2224/78—Apparatus for connecting with wire connectors
- H01L2224/7825—Means for applying energy, e.g. heating means
- H01L2224/783—Means for applying energy, e.g. heating means by means of pressure
- H01L2224/78301—Capillary
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/8512—Aligning
- H01L2224/85148—Aligning involving movement of a part of the bonding apparatus
- H01L2224/85169—Aligning involving movement of a part of the bonding apparatus being the upper part of the bonding apparatus, i.e. bonding head, e.g. capillary or wedge
- H01L2224/8518—Translational movements
- H01L2224/85181—Translational movements connecting first on the semiconductor or solid-state body, i.e. on-chip, regular stitch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/852—Applying energy for connecting
- H01L2224/85201—Compression bonding
- H01L2224/85205—Ultrasonic bonding
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
［発明の技術分野Ｊ
この発明は、例えばＩＣ（あるいはＬＳＩ）チップの電
極部とパッケージ導体部とのワイヤボンディングを超音
波振動エネルギーを用いて行なう際、ボンディングが正
常に行われたか否かを判定するためのボンディング検査
方式に関する。[Detailed Description of the Invention] [Technical Field of the Invention J] The present invention provides a method for properly bonding when performing wire bonding between, for example, an electrode part of an IC (or LSI) chip and a package conductor part using ultrasonic vibration energy. The present invention relates to a bonding inspection method for determining whether bonding has been performed.
一般に、半導体基板（ウェハ）にパターン形成された後
、個々に分割されて形成されたＩＣチップは、例えば第
５図に示すように、リードフレームのベッド１１にダイ
ボンディングされた後、ボンディング装置の台１０に載
置されて所定の温度に加熱され、ＩＣチップ１２のポン
ディングパッド（電極部）１２ａとリードフレームのイ
ンナーリード部１３とがボンディングワイヤ１４を用い
て接続される。In general, after forming a pattern on a semiconductor substrate (wafer), IC chips that are formed by being divided into individual chips are die-bonded to a bed 11 of a lead frame, for example, as shown in FIG. It is placed on a stand 10 and heated to a predetermined temperature, and bonding pads (electrode portions) 12a of the IC chip 12 and inner lead portions 13 of the lead frame are connected using bonding wires 14.
そして、ＩＣチップ１２に形成されている各素子の電極
が外部に導出される。その後、上記ベッド１１゜ＩＣチ
ップ１２．インナーリード部１３．ボンディングワイヤ
１４等が、樹脂あるいはセラミック等の外囲器に封止さ
れて完成される。Then, the electrodes of each element formed on the IC chip 12 are led out. After that, the bed 11° IC chip 12. Inner lead part 13. The bonding wire 14 and the like are sealed in an envelope made of resin, ceramic, or the like.
第６図は、上記ＩＣチップ１２の電極部１２ａとインナ
ーリード部１３とを超音波の振動エネルギーによってボ
ンディングする超音波ボンディング装置について説明す
るためのもので、図において１５は超音波発振器、１６
はこの超音波発振器１５によって駆動され超音波振動す
るキャピラリー、１７は金（ＡＵ）、アルミニウム（Ａ
１）等から成るボンディングワイヤである。電極部１２
ａとインナーリード部１３とのワイヤボンディングは、
先ず第６図（ａ）に示すように、キャピラリー１６をＩ
Ｃチップ１２の電極部１２ａに接触させた状態で超音波
発振器１５によってキャピラリー１６を超音波振動させ
、ボンディングワイヤ１７の一端を圧接させる。次に、
第６図（ｂ）に示すように、ボンディングワイヤ１７を
導出しつつ、上記キャピラリー１６をリードフレームの
インナーリード部１３上に移動し、このインナーリード
部１３と接触した状態で超音波発振器１５によりキャピ
ラリー１６を超音波振動させ、ボンディングワイヤ１７
とインナーリード部１３とを圧接している。FIG. 6 is for explaining an ultrasonic bonding apparatus for bonding the electrode portion 12a of the IC chip 12 and the inner lead portion 13 using ultrasonic vibration energy.
17 is a capillary that is driven by this ultrasonic oscillator 15 and vibrates ultrasonically;
1), etc. Electrode part 12
The wire bonding between a and the inner lead part 13 is as follows:
First, as shown in FIG. 6(a), the capillary 16 is
The capillary 16 is ultrasonically vibrated by the ultrasonic oscillator 15 while in contact with the electrode portion 12a of the C-chip 12, and one end of the bonding wire 17 is pressed into contact with the capillary 16. next,
As shown in FIG. 6(b), while leading out the bonding wire 17, the capillary 16 is moved onto the inner lead part 13 of the lead frame, and while in contact with the inner lead part 13, the capillary 16 is activated by the ultrasonic oscillator 15. The capillary 16 is vibrated ultrasonically, and the bonding wire 17
and the inner lead portion 13 are pressed together.
ところで、上述したようなボンディングの際、ボンディ
ングワイヤ１１とＩＣチップ１２の電極部１２ａ１ある
いはインナーリード部１３とが完全に接続されなかった
り、ボンディングワイヤ１１が途中で切れたりすること
がある。このような不良はボンディングの最中には分ら
ないため、不良品を次の工程に回してしまうことになる
。従って、ボンディングが正常に行われたか否かを後の
工程で検査する必要がある。また、上述したような不良
がボンディング装置の異常状態により発生している場合
には、不良品が次々に生産されることになり、大きな問
題となる。By the way, during the above-described bonding, the bonding wire 11 and the electrode portion 12a1 or the inner lead portion 13 of the IC chip 12 may not be completely connected, or the bonding wire 11 may be broken in the middle. Since such defects are not detected during bonding, the defective products are passed on to the next process. Therefore, it is necessary to check whether the bonding was performed normally in a later process. Further, if the above-mentioned defects occur due to an abnormal state of the bonding device, defective products will be produced one after another, which will cause a big problem.
［発明の目的］
この発明は上記のような事情に鑑みてなされたもので、
その目的とするところは、ボンディング作業中にボンデ
ィングが正常に行われたか否かを検査でき、作業能率の
向上およびボンディング装置の異常状態による無駄を省
けるボンディング検査方式を提供することである。[Object of the invention] This invention was made in view of the above circumstances,
The purpose is to provide a bonding inspection method that can inspect whether or not bonding has been performed normally during bonding work, improve work efficiency, and eliminate waste due to abnormal conditions of the bonding device.
［発明の概要］
すなわち、この発明においては、上記の目的を達成する
ために、ボンディングの際にキャピラリーに流れる高周
波電流の波形を検出し、この高周波電流波形の形状とそ
の電流強度とに基づいてボンディングが正常に行われた
か否かを検査するようにしている。[Summary of the Invention] That is, in order to achieve the above object, the present invention detects the waveform of a high-frequency current flowing through a capillary during bonding, and detects the waveform of a high-frequency current flowing through a capillary based on the shape of the high-frequency current waveform and its current intensity. It is checked whether bonding was performed normally.
７°【発明の実施例］
以下、この発明の一実施例について図面を参照して説明
する。この発明は次のような点に着目してなされている
。すなわち、超音波発振器によりキャピラリーを駆動し
てボンディングを行なう際、このキャピラリーに流れる
高周波電流の波形が正常なボンディングの場合と異常ボ
ンディングの場合とで異なっている。従って、この高周
波電流の波形を検出して基準となる波形と比較すること
により、ボンディングが正常に行われたが否かを知るこ
とが出来る。7° [Embodiment of the Invention] An embodiment of the present invention will be described below with reference to the drawings. This invention has been made by focusing on the following points. That is, when bonding is performed by driving a capillary with an ultrasonic oscillator, the waveform of the high frequency current flowing through the capillary is different between normal bonding and abnormal bonding. Therefore, by detecting the waveform of this high-frequency current and comparing it with a reference waveform, it is possible to know whether or not bonding has been performed normally.
第２図は上記高周波電流の各状態における波形を示して
いる。第２図において、実線は正常なボンディングが行
われた場合、破線は無負荷の場合、一点鎖線はボンディ
ングワイヤが切れて空打ちした場合の高周波電流波形で
ある。FIG. 2 shows the waveform of the high frequency current in each state. In FIG. 2, the solid line shows the high-frequency current waveform when normal bonding is performed, the broken line shows the high-frequency current waveform when there is no load, and the one-dot chain line shows the high-frequency current waveform when the bonding wire is broken and the bonding wire is broken.
次に、上記各高周波電流の波形からボンディングが正常
に行われたか否かを検出するための回路構成について第
１図を参照しつつ説明する。超音波発振器１５の出力は
、Ａ／Ｄ変換器１８および制御回路２０にそれぞれ供給
される。上記Ａ／Ｄ変換器１８による高周波電流のアナ
ログ／ディジタル変換出力は、メモリ２１に供給されて
記憶され、このメモリ２１の記憶データが加算器２２お
よび除算！１２３に供給される。上記加算器２２の加算
出力は除算器２３に供給され、この除算器２３の演算出
力は正規化回路２４に供給されて正規化される。そして
、この正規化回路２４の出力と基準パターンメモリ２５
に記憶された基準パターンとの差が差検出回路２６によ
って検出される。上記差検出回路２Ｇによる基準パター
ンデータと正規化回路２４から出力される超音波発振器
１５からのボンディングデータとの差出力は、加算８２
７に供給されて加算される。そして、前記加算器２２お
よび加算器２７の加算出力がそれぞれ判定回路２９に供
給され、この判定回路２９からボンディングが正常に行
われたか否かを判定出力ＯＵＴとして得るようにして成
る。なお、上記Ａ／Ｄ変換器１Ｂ、メモリ２１．加算器
２２．除算器２３．正規化回路２４．基準パターンメモ
リ２５．差検出回路２６゜加算器２７、および判定回路
２９はそれぞれ、上記制御回路２０の出力によって制御
される。Next, a circuit configuration for detecting whether or not bonding has been normally performed based on the waveforms of the respective high-frequency currents will be described with reference to FIG. 1. The output of the ultrasonic oscillator 15 is supplied to an A/D converter 18 and a control circuit 20, respectively. The analog/digital conversion output of the high frequency current by the A/D converter 18 is supplied to the memory 21 and stored therein, and the data stored in this memory 21 is sent to the adder 22 and divided! 123. The addition output of the adder 22 is supplied to a divider 23, and the calculation output of the divider 23 is supplied to a normalization circuit 24 for normalization. The output of this normalization circuit 24 and the reference pattern memory 25
A difference detection circuit 26 detects the difference from the reference pattern stored in the reference pattern. The difference output between the reference pattern data by the difference detection circuit 2G and the bonding data from the ultrasonic oscillator 15 output from the normalization circuit 24 is calculated by addition 82.
7 and is added. The addition outputs of the adder 22 and the adder 27 are each supplied to a determination circuit 29, from which a determination output OUT indicating whether or not bonding has been performed normally is obtained. Note that the A/D converter 1B, memory 21. Adder 22. Divider 23. Normalization circuit 24. Reference pattern memory 25. The difference detection circuit 26, the adder 27, and the determination circuit 29 are each controlled by the output of the control circuit 20.
次に、上記のような構成において、動作を説明する。ボ
ンディング時に、第３図に示すように、超音波発振器１
５から出力される高周波電流の微少時間開隔ｔ（１〜ｎ
）における電流強度を、Ａ／Ｄ変換器１８によりアナロ
グ／ディジタル変換して、メモリ２１に順次記憶する。Next, the operation in the above configuration will be explained. During bonding, as shown in Figure 3, the ultrasonic oscillator 1
The minute time interval t(1 to n
) is converted from analog to digital by the A/D converter 18 and sequentially stored in the memory 21.
このメモリ２１に記憶された各時間（ｔｌ〜ｔｎ）にお
ける電流強度は加算器２２によって加算され、この加算
値によって各時間ｔ１〜ｔｎにおける各電流強度が除算
器２３で除算される。また、上記加算器２２の加算出力
は判定回路２９に供給される。そして、上記除算器２３
の出力が正規化回路２４に供給されて正規化パターンが
作成される。上記正規化回路２４による正規化パターン
と、予め設定して基準パターンメモリ２５に記憶した正
常なボンディングが行われた際の正規化パターンとの差
が差検出回路２６により各時間（ｔ１〜ｔｎ）の各々の
点で検出される。そして、上記差検出回路２６の出力を
加算器２７で加算することにより求められた相関値が判
定回路２９に供給される。判定回路２９では、上記加算
！１２７による相関値が所定の値以下で、かつ上記加算
器２２による加算値（高周波電流の積分値に相当する）
が所定の範囲に入っている時に、正常なボンディングが
行われたと判断する。The current intensities at each time (tl to tn) stored in this memory 21 are added by an adder 22, and the current intensities at each time t1 to tn are divided by a divider 23 by this added value. Further, the addition output of the adder 22 is supplied to a determination circuit 29. Then, the divider 23
The output is supplied to the normalization circuit 24 to create a normalization pattern. The difference between the normalized pattern by the normalization circuit 24 and the normalized pattern set in advance and stored in the reference pattern memory 25 when normal bonding is performed is determined by the difference detection circuit 26 at each time (t1 to tn). is detected at each point. Then, a correlation value obtained by adding the outputs of the difference detection circuit 26 in an adder 27 is supplied to a determination circuit 29. The determination circuit 29 performs the above addition! 127 is less than or equal to a predetermined value, and the added value by the adder 22 (corresponds to the integrated value of high-frequency current)
When the value falls within a predetermined range, it is determined that normal bonding has been performed.
なお、ＩＣチップ１２の電極部１２ａにボンディングす
る時と、インナーリード部１３にボンディングする時で
高周波電流の波形が興なる場合には、前記基準パターン
メモリ２５に各々の基準パターンを用意するとともに、
加算器２２および２１の加算値の基準値を各々用意して
おけばよい。Note that if the waveform of the high-frequency current occurs when bonding to the electrode portion 12a of the IC chip 12 and when bonding to the inner lead portion 13, respective reference patterns are prepared in the reference pattern memory 25, and
It is sufficient to prepare reference values for the addition values of adders 22 and 21, respectively.
このような構成によれば、ボンディング作業中にボンデ
ィングが正常に行われたか否かを判定できるので、不良
品を次の工程に回すことがなく作業能率を向上できる。According to such a configuration, it is possible to determine whether or not bonding has been performed normally during the bonding operation, so that it is possible to improve work efficiency without passing defective products to the next process.
また、ボンディング装置の異常状態による不良もすぐに
発見でき、作業の無駄がなくなる。In addition, defects caused by abnormal conditions in the bonding device can be detected immediately, eliminating wasted work.
第４図は、この発明の他の実施例を示している。FIG. 4 shows another embodiment of the invention.
すなわち、ボンディングの不良が発生する度にボンディ
ング装置を停止して不良ＩＣを取り除いていると作業能
率が低下するため、判定回路２９により異常が発見され
た時に、これをメモリに記憶（あるいはプリンタ等の出
力機器で出力）するとともに、ボンディングワイヤを破
損するようにしている。第４図において、前記第１図と
同一構成部分には同じ符号を付してその詳細な説明は省
略する。判定回路２９の出力は、判定結果メモリ３０に
供給されるとともに、ボンディングワイヤ破損機構３１
に供給される。そして、ボンディングの正否を上記判定
結果メモリ３０に記録するとともに、不良が発生した時
にはワイヤ破損機構３１によってボンディングワイヤを
切断、あるいはハンマー等でワイヤを叩くことによりボ
ンディングワイヤを破壊してから次の工程に順次送るよ
うにしている。In other words, if the bonding device is stopped and the defective IC is removed every time a bonding defect occurs, work efficiency will decrease. Therefore, when an abnormality is discovered by the judgment circuit 29, it is stored in memory (or printed on a printer, etc.). output device) and damage the bonding wire. In FIG. 4, the same components as those in FIG. 1 are given the same reference numerals, and detailed explanation thereof will be omitted. The output of the determination circuit 29 is supplied to the determination result memory 30 and also to the bonding wire breakage mechanism 31.
supplied to Then, the success or failure of the bonding is recorded in the judgment result memory 30, and if a defect occurs, the bonding wire is broken by cutting it by the wire breaking mechanism 31 or by hitting the wire with a hammer or the like, and then the next step is carried out. I am trying to send them sequentially.
従って、このような構成によれば、ボンディング作業の
流れを止めることなく作業が行なえ、かつ不良品を誤っ
て出荷してしまうこともない。Therefore, with such a configuration, the bonding work can be performed without stopping the flow of the bonding work, and defective products will not be shipped by mistake.
［発明の効果〕
以上説明したようにこの発明によれば、ボンディング作
業中にボンディングが正常に行われたか否かを検査でき
、作業能率の向上およびボンディング装置の異常状態に
よる無駄を省けるボンディング検査方式が得られる。[Effects of the Invention] As explained above, according to the present invention, there is provided a bonding inspection method that can inspect whether or not bonding has been performed normally during bonding work, improve work efficiency, and eliminate waste due to abnormal conditions of the bonding device. is obtained.
第１図ないし第３図はそれぞれこの発明の一実施例に係
わるボンディング検査方式について説明するための図、
第４図はこの発明の他の実施例ついて説明するためのブ
ロック図、第５図および第６図はそれぞれ従来のボンデ
ィング装置について説明するための図である。
１０・・・ボンディング装置の台、１１・・・ベッド、
１２・・・ＩＣチップ、１２ａ・・・電極部、１３・・
・インナーリード部、１５・・・超音波発振器、１６・
・・キャピラリー、１７・・・ボンディングワイヤ、１
８・・・Ａ／Ｄ変換器、２０・・・制御回路、２１・・
・メモリ、２２．２７・・・加算器、２３・・・除算器
、２４・・・正規化回路、２５・・・基準パターンメモ
リ、２６・・・差検出回路、２９・・・判定回路、３０
・・・判定結果メモリ、３１・・・ボンディングワイヤ
破損機構。
出願人代理人 弁理士 鈴江武彦
第２図
嶋’ｆ’ａ’ｌ Ｔ−
第３図1 to 3 are diagrams for explaining a bonding inspection method according to an embodiment of the present invention, respectively;
FIG. 4 is a block diagram for explaining another embodiment of the present invention, and FIGS. 5 and 6 are diagrams for explaining a conventional bonding apparatus, respectively. 10... Bonding device stand, 11... Bed,
12...IC chip, 12a...electrode part, 13...
・Inner lead part, 15... Ultrasonic oscillator, 16・
... Capillary, 17 ... Bonding wire, 1
8... A/D converter, 20... Control circuit, 21...
- Memory, 22.27... Adder, 23... Divider, 24... Normalization circuit, 25... Reference pattern memory, 26... Difference detection circuit, 29... Judgment circuit, 30
... Judgment result memory, 31... Bonding wire damage mechanism. Applicant's agent Patent attorney Takehiko Suzue Figure 2 Shima'f'a'l T- Figure 3
Claims (6)
ディングを超音波振動エネルギーを用いて行なう際、ボ
ンディング時の高周波電流波形に基づいてボンディング
が正常に行なわれたか否かを判定することを特徴とする
ボンディング検査方式。(1) When bonding the electrode part of the IC chip and the package conductor part using ultrasonic vibration energy, it is determined whether or not the bonding was performed normally based on the high-frequency current waveform at the time of bonding. A bonding inspection method that uses
電流波形として、その形状と電流強度とを用いることを
特徴とする特許請求の範囲第１項記載のボンディング検
査方式。(2) The bonding inspection method according to claim 1, wherein the shape and current intensity are used as the high-frequency current waveform for determining whether the bonding is correct or not.
て微少時間間隔で電流強度を読取り正規化したものを用
いることを特徴とする特許請求の範囲第２項記載のボン
ディング検査方式。(3) The bonding inspection method according to claim 2, wherein the shape of the high-frequency current waveform is obtained by reading and normalizing the current intensity at minute time intervals with respect to the time axis.
対して微少時間間隔で電流強度を読取り正規化した値を
加算したものを用いることを特徴とする特許請求の範囲
第２項記載のボンディング検査方式。(4) The bonding according to claim 2, wherein the current intensity of the high-frequency current waveform is obtained by adding a value obtained by reading and normalizing the current intensity at minute time intervals with respect to the time axis. Inspection method.
高周波電流波形と予め設定した基準となる波形との相関
値が所定の値以下で、かつ高周波電流の強度が所定の範
囲内にある時のみ正常と判断することを特徴とする特許
請求の範囲第１項記載のボンディング検査方式。(5) As a condition for determining whether the bonding is correct or not, it is normal only when the correlation value between the high-frequency current waveform and a preset reference waveform is less than a predetermined value, and the intensity of the high-frequency current is within a predetermined range. The bonding inspection method according to claim 1, wherein the bonding inspection method determines that.
記録するとともに、ボンディングワイヤを破損すること
を特徴とする特許請求の範囲第１項記載のボンディング
検査方式。(6) The bonding inspection method according to claim 1, wherein when the bonding is determined to be defective, this is recorded and the bonding wire is damaged.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60079956A JPS61237438A (en) | 1985-04-15 | 1985-04-15 | Inspection of bonding |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60079956A JPS61237438A (en) | 1985-04-15 | 1985-04-15 | Inspection of bonding |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61237438A true JPS61237438A (en) | 1986-10-22 |
Family
ID=13704756
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60079956A Pending JPS61237438A (en) | 1985-04-15 | 1985-04-15 | Inspection of bonding |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61237438A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5608855A (en) * | 1991-09-09 | 1997-03-04 | Hitachi, Ltd. | Method of and system for displaying three-dimensional curve on two-dimensional display device |
| JP2011113983A (en) * | 2009-11-23 | 2011-06-09 | Toyota Motor Corp | Method of inspecting tool and method of manufacturing inverter |
-
1985
- 1985-04-15 JP JP60079956A patent/JPS61237438A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5608855A (en) * | 1991-09-09 | 1997-03-04 | Hitachi, Ltd. | Method of and system for displaying three-dimensional curve on two-dimensional display device |
| JP2011113983A (en) * | 2009-11-23 | 2011-06-09 | Toyota Motor Corp | Method of inspecting tool and method of manufacturing inverter |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| EP1469319B1 (en) | Flip-chip mounting method and mounting apparatus of electronic part | |
| US4373653A (en) | Method and apparatus for ultrasonic bonding | |
| JPS644338B2 (en) | ||
| US5836071A (en) | Method to produce known good die using temporary wire bond, die attach and packaging | |
| JPH02187286A (en) | Automatic wire welder | |
| JPS59134841A (en) | On-line inspecting method and system for bonding to electronic part | |
| JPS61237438A (en) | Inspection of bonding | |
| JPS61237439A (en) | Inspection of bonding | |
| US7654434B2 (en) | Method, device and system for bonding a semiconductor element | |
| JPS61237440A (en) | Inspection of bonding | |
| US4661771A (en) | Method of screening resin-sealed semiconductor devices | |
| JPH06349913A (en) | Non-contact monitoring method for burn-in test | |
| US7080771B2 (en) | Method for checking the quality of a wedge bond | |
| JPH01217931A (en) | Flip chip | |
| JP2000124280A (en) | Semiconductor devices applicable to wafer burn-in | |
| Seppänen et al. | Ultrasonic Wire Bond Outlier Classification | |
| JPH04239145A (en) | Marking method for semiconductor integrated circuit device | |
| JPH01145566A (en) | Inspecting apparatus of bonded state | |
| KR100548002B1 (en) | Method for detecting component pollution using wire bonding monitering system | |
| JPS61294830A (en) | Automatic wire bonding apparatus | |
| JP2002043359A (en) | Wire bonding device | |
| KR980005960A (en) | Apparatus and method for removing bad material in die bonding process | |
| US20030210068A1 (en) | Apparatus of testing semiconductor | |
| JPS63156334A (en) | Apparatus for assembling semiconductor element | |
| JP2004053326A (en) | Inspecting method for semiconductor device |