KR20000071716A - Bonding failure inspection method and apparatus for bump bonding - Google Patents

Bonding failure inspection method and apparatus for bump bonding Download PDF

Info

Publication number
KR20000071716A
KR20000071716A KR1020000020225A KR20000020225A KR20000071716A KR 20000071716 A KR20000071716 A KR 20000071716A KR 1020000020225 A KR1020000020225 A KR 1020000020225A KR 20000020225 A KR20000020225 A KR 20000020225A KR 20000071716 A KR20000071716 A KR 20000071716A
Authority
KR
South Korea
Prior art keywords
ball
wire
semiconductor chip
signal
voltage
Prior art date
Application number
KR1020000020225A
Other languages
Korean (ko)
Inventor
데라카도요시미츠
가토후미히코
Original Assignee
후지야마 겐지
가부시키가이샤 신가와
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 후지야마 겐지, 가부시키가이샤 신가와 filed Critical 후지야마 겐지
Publication of KR20000071716A publication Critical patent/KR20000071716A/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
    • H01L24/741—Apparatus for manufacturing means for bonding, e.g. connectors
    • H01L24/742—Apparatus for manufacturing bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1133—Manufacturing methods by local deposition of the material of the bump connector in solid form
    • H01L2224/1134—Stud bumping, i.e. using a wire-bonding apparatus
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/741—Apparatus for manufacturing means for bonding, e.g. connectors
    • H01L2224/742—Apparatus for manufacturing bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/78—Apparatus for connecting with wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/78—Apparatus for connecting with wire connectors
    • H01L2224/7825—Means for applying energy, e.g. heating means
    • H01L2224/78268—Discharge electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/78—Apparatus for connecting with wire connectors
    • H01L2224/7825—Means for applying energy, e.g. heating means
    • H01L2224/783—Means for applying energy, e.g. heating means by means of pressure
    • H01L2224/78301—Capillary
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/78—Apparatus for connecting with wire connectors
    • H01L2224/786—Means for supplying the connector to be connected in the bonding apparatus
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85009—Pre-treatment of the connector or the bonding area
    • H01L2224/8503—Reshaping, e.g. forming the ball or the wedge of the wire connector
    • H01L2224/85035—Reshaping, e.g. forming the ball or the wedge of the wire connector by heating means, e.g. "free-air-ball"
    • H01L2224/85045—Reshaping, e.g. forming the ball or the wedge of the wire connector by heating means, e.g. "free-air-ball" using a corona discharge, e.g. electronic flame off [EFO]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/851—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector the connector being supplied to the parts to be connected in the bonding apparatus
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/852—Applying energy for connecting
    • H01L2224/85201—Compression bonding
    • H01L2224/85205—Ultrasonic bonding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/859—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector involving monitoring, e.g. feedback loop
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Abstract

범프본딩에 있어서의 볼 불착을 단시간에 검출할 수 있다.Ball non-adherence in bump bonding can be detected in a short time.

볼(3a)을 반도체칩(5)에 접속한 후로부터 와이어(3)를 볼(3a)의 부착부분으로부터 절단하기까지의 기간에, 와이어(3)에 전압을 인가하는 전원(16, 17)과, 볼 불착의 유무에 의한 상기 기간중의 전압의 변화를 검출함으로써 볼 불착의 유무를 판정하는 컴퓨터(20)를 구비한다.Power supply 16, 17 for applying a voltage to wire 3 in a period from connecting ball 3a to semiconductor chip 5 until cutting wire 3 from the attachment portion of ball 3a. And a computer 20 for determining the presence or absence of ball failure by detecting a change in the voltage during the period caused by the presence or absence of ball failure.

Description

범프본딩에 있어서의 불착검사방법 및 장치{BONDING FAILURE INSPECTION METHOD AND APPARATUS FOR BUMP BONDING}Non-bonding inspection method and apparatus in bump bonding TECHNICAL FIELD [BONING FAILURE INSPECTION METHOD AND APPARATUS FOR BUMP BONDING}

본 발명은 캐필러리에 끼워통하는 와이어의 선단에 볼을 형성하고, 이 볼을 범프로서 반도체칩 상에 본딩하는 범프본딩에 있어서의 불착 검사방법 및 장치에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a method and an apparatus for inspecting non-adherence in bump bonding in which a ball is formed at a tip of a wire inserted into a capillary and the ball is bonded on a semiconductor chip as a bump.

범프본딩방법은, 일반적으로 도 4에 도시하는 공정에 의해 행해진다. 먼저 클램퍼(1)가 닫힌 상태에서, 캐필러리(2)에 끼워통하게 된 와이어(3)의 선단에 방전전극(4)으로부터의 방전에 의하여 볼(3a)을 형성한다. 계속해서 도 4(a)에 도시하는 바와 같이, 클램퍼(1)가 개방되면, 와이어(3)가 도시하지 않은 백텐션기구에 의해 적당한 힘으로 상방으로 되돌려진다. 다음에 도 4(b)에 도시하는 바와 같이, 캐필러리(2)가 하강하여 볼(3a)을 반도체 칩(5)의 패드전극(6) 표면을 누르게 한다. 그 후는 캐필러리(2)를 유지한 초음파 혼(도시 생략)에 의해 초음파를 인가하면서 캐필러리(2)로 볼(3a)을 가압하고, 변형시켜서 패드전극(6)에 접속한다.The bump bonding method is generally performed by the process shown in FIG. First, in the state where the clamper 1 is closed, the ball 3a is formed by the discharge from the discharge electrode 4 at the tip of the wire 3 inserted into the capillary 2. Subsequently, as shown in Fig. 4A, when the clamper 1 is opened, the wire 3 is returned upward by an appropriate force by a back tension mechanism (not shown). Next, as shown in FIG. 4B, the capillary 2 is lowered so that the ball 3a is pressed against the surface of the pad electrode 6 of the semiconductor chip 5. Thereafter, while applying an ultrasonic wave by an ultrasonic horn (not shown) holding the capillary 2, the ball 3a is pressed by the capillary 2, deformed, and connected to the pad electrode 6.

다음에 도 4(c)에 도시하는 바와 같이, 캐필러리(2) 및 클램퍼(1)가 함께 상승하여, 다음 볼(3a)을 형성하기 위한 와이어(3)(테일)을 풀어내면서 클램퍼(1)가 폐쇄된다. 다시 캐필러리(2) 및 클램퍼(1)가 함께 상승하고, 도 4(d)에 도시하는 바와 같이 와이어(3)가 볼(3a)의 부착부분으로부터 절단된다. 이것에 의해 범프(7)가 형성된다. 더우기 이 종류의 범프본딩방법으로서, 예를 들면 일본 특개소 54 - 2662호 공보, 일본 특공평 4 - 41519호 공보, 일본 특개평 7 - 86286호 공보 등에 표시되는 것을 들을 수 있다.Next, as shown in Fig. 4 (c), the capillary 2 and the clamper 1 are raised together to release the wire 3 (tail) for forming the next ball 3a. 1) is closed. Again, the capillary 2 and the clamper 1 rise together, and the wire 3 is cut from the attachment portion of the ball 3a as shown in Fig. 4 (d). As a result, the bumps 7 are formed. Moreover, as this kind of bump bonding method, what is displayed on Japanese Unexamined-Japanese-Patent No. 54-2662, Japanese Unexamined-Japanese-Patent No. 4-41519, Japanese Unexamined-Japanese-Patent No. 7-86286, etc. are mentioned, for example.

범프본딩에 있어서의 범프(7)의 불착(볼(3a)과 패드전극(6) 사이의 불착)으로서, 도 5 (a),도 5 (b)에 도시하는 현상이 있다. 도 5(a)는 상기한 도 4(c)의 공정에 있어서의 불착, 도 5(b)는 도 4(d)의 공정에 있어서의 불착을 도시한다. 즉 도 4(c)에 도시하는 바와 같이 캐필러리(2)가 상승할 때, 도 5(a)에 도시하는 바와 같이 볼(3a)이 벗겨진 상태(볼(3a)이 패드전극(6)에 접속되지 않는 상태), 또 도 4(d)와 같이 와이어(3)을 절단할 때, 도 5(b)와 같이 볼(3a)이 벗겨져버린 상태가 있다.There is a phenomenon shown in Figs. 5 (a) and 5 (b) as non-adherence of the bump 7 (non-adhesion between the ball 3a and the pad electrode 6) in bump bonding. Fig. 5 (a) shows the failure in the process of Fig. 4 (c), and Fig. 5 (b) shows the failure in the process of Fig. 4 (d). That is, when the capillary 2 rises as shown in FIG. 4 (c), as shown in FIG. 5 (a), the ball 3a is peeled off (the ball 3a is the pad electrode 6). When the wire 3 is cut off as shown in Fig. 4 (d), the ball 3a is peeled off as shown in Fig. 5 (b).

범프본딩의 경우에는 와이어(3)의 재질로서 땜납 등과 같이 금선보다 연한 것도 사용된다. 와이어(3)의 땜납재질과 반도체칩(5)의 패드전극(6) 표면의 재질이 익숙해지지 않으면(접합성이 부량), 도 5(b)의 현상보다 도 5(a)의 현상이 발생하기 쉽다. 도 5(a), 도 5(b)와 같은 불착은, 도 4(d)와 같이 테일(3b)이 형성되지 않으므로, 예를 들면 일본국 특개공 54 - 35065호 공보에 표시하는 방법에 의해, 도 4(a)에 도시하는 볼(3a)의 형성시에 검출할 수가 있다. 그러나 범프본딩에 있어서는 상기한 바와 같이 도 5(b)의 현상보다 도 5(a)의 현상이 발생되기 쉽다. 이 도 5(a)의 현상은, 상기 방법으로는 즉시 검출할 수 없다. 종래 범프본딩에 있어서의 범프의 불착을 검출하는 방법 및 장치는 존재하지 않는다.In the case of bump bonding, a material softer than gold wire such as solder or the like is used as a material of the wire 3. If the solder material of the wire 3 and the material of the surface of the pad electrode 6 of the semiconductor chip 5 are not used (adequate adhesion), the phenomenon of FIG. 5 (a) may occur rather than the phenomenon of FIG. 5 (b). easy. 5A and 5B, the tail 3b is not formed as shown in FIG. 4 (d). Thus, for example, by the method shown in Japanese Patent Laid-Open No. 54-35065. Can be detected at the time of formation of the ball 3a shown in Fig. 4A. However, in bump bonding, the phenomenon of FIG. 5A is more likely to occur than the phenomenon of FIG. 5B as described above. This phenomenon of FIG. 5A cannot be detected immediately by the said method. There is no method and apparatus for detecting bump failure in conventional bump bonding.

와이어본딩에 있어서는, 와이어의 불착검출방법으로서, 일본국 특공평1- 58868 호 공보, 일본국 특허 제 2617351호 공보 등에 표시되는 것이 알려져 있다. 이 와이어본딩에 의한 불착검출의 장치를 도 6에 도시한다. 도 6은 반도체칩(5)이 은페이스트 등의 도전성(導電性) 접착제로 리드프레임(10)에 고착된 공작물에 적용한 예를 표시한다. 반도체칩(5)이 고착된 리드프레임(10)은 시료대(11)에 위치결정 고정되고, 반도체칩(5)의 패드전극(6)은, 반도체칩(5)의 내부저항(Rd), 리드프레임 (10)을 겨쳐서 어스에 접속된다. 또한 반도체칩(5)이 절연물로 이루어지는 기판등에 고착되어 있는 경우에는, 반도체칩(5)은 미리 기판상에 설치된 배선패턴에 도통접속되고, 이 배선패턴을 통하여 어스에 접속된다.In wire bonding, it is known to be displayed in Japanese Unexamined Patent Publication No. Hei 1-58868, Japanese Patent No. 2617351, or the like as a method for detecting the non-bonding of wires. Fig. 6 shows a device for non-detection by this wire bonding. FIG. 6 shows an example in which the semiconductor chip 5 is applied to a workpiece fixed to the lead frame 10 with a conductive adhesive such as silver paste. The lead frame 10 to which the semiconductor chip 5 is fixed is fixed to the sample stage 11, and the pad electrode 6 of the semiconductor chip 5 includes the internal resistance Rd of the semiconductor chip 5, The lead frame 10 is connected to the earth while facing each other. In addition, when the semiconductor chip 5 is stuck to the board | substrate etc. which consist of an insulator, the semiconductor chip 5 is electrically connected to the wiring pattern previously provided on the board | substrate, and is connected to earth through this wiring pattern.

반도체칩(5)과 리드프레임(10)에 접속되는 와이어(3)는 스풀(12)에 감아돌려져 있으며, 일단은 캐필러리(2)에 끼워통하고, 타단은 단자(13)에 접속되어 있다. 단자(13)는 스위치(SW1)의 공통접점(C)에 접속되고, 스위치(SW1)의 상시폐쇄접점 (NC)은 어스되어 있다. 스위치(SW1)의 상시개방접점(NO)은 검출기(14) 및 저항(15)의 일단에 접속되어 있으며, 저항(15)의 타단은 스위치(SW2)에 의해 2개의 전원(16, 17)에 선택적으로 접속된다. 2개의 전원(16, 17)을 설치한 것은 반도체칩 (5)의 패드전극(6)과 어스 사이에 다이오드특성이 있기 때문에 반도체칩(5)에 의해 극성(순차 이송인지 반대이송인지에 따른 극성)이 상이하기 때문이고, 스위치(SW2)에 의해 극성을 반전시켜서 대응시킨다.The wire 3 connected to the semiconductor chip 5 and the lead frame 10 is wound around the spool 12, one end of which is inserted into the capillary 2, and the other end of which is connected to the terminal 13. have. The terminal 13 is connected to the common contact C of the switch SW1, and the normally closed contact NC of the switch SW1 is earthed. The normally open contact point NO of the switch SW1 is connected to one end of the detector 14 and the resistor 15, and the other end of the resistor 15 is connected to the two power supplies 16 and 17 by the switch SW2. Is optionally connected. Since the two power sources 16 and 17 are provided with a diode characteristic between the pad electrode 6 and the earth of the semiconductor chip 5, the polarity (polarity according to whether the sequential transfer or the reverse transfer is performed by the semiconductor chip 5). Is different, and the polarity is reversed by the switch SW2 to correspond.

상기 스위치(SW1)의 변환의 타이밍은, 도 7에 도시하는 본딩상태에서 행해진다. 먼저, 캐필러리(2)의 하단에 설치된 와이어(3)의 선단에 방전전극(4)로부터의 방전에 의해 볼(3a)이 형성된다. 다음에 캐필러리(2)가 하강하고, 볼(3a)은 반도체칩(5)의 패드전극(6)에 제 1 본딩된다. 그 후 캐필러리(2)는 상승하고, 리드 (10a)의 제 2 본드점의 상방에 이동하고, 재차 하강한다. 이 사이에 스위치(SW1)는 상시개방접점(NO)에 접속된다. 이 경우, 볼(3a)이 패드전극(6)에 접속되어 있으면, 상기한 바와 같이 패드전극(6)은 저항(Rd), 리드프레임(10)을 거쳐서 어스되어 있으므로, 전원(16 또는 17)으로부터 스위치(SW2), 저항(15), 스위치(SW1), 단자(13)을 통과하여 와이어(3)에 전류가 흐르고, 검출기(14)에는 전류가 흐르지 않는다. 혹시, 볼(3a)이 패드전극(6)에 접속되어 있지 않으면, 와이어(3)에는 전류가 흐르지 않으며, 검출기(14)에 전류가 흘러, 검출기(14)로부터 와이어 접속불량신호가 출력된다.The timing of conversion of the switch SW1 is performed in the bonding state shown in FIG. First, the ball 3a is formed by the discharge from the discharge electrode 4 at the tip of the wire 3 provided at the lower end of the capillary 2. Next, the capillary 2 is lowered, and the ball 3a is first bonded to the pad electrode 6 of the semiconductor chip 5. Thereafter, the capillary 2 moves up, moves above the second bond point of the lead 10a, and descends again. In the meantime, the switch SW1 is connected to the normally open contact NO. In this case, if the ball 3a is connected to the pad electrode 6, the pad electrode 6 is earthed through the resistor Rd and the lead frame 10 as described above, so that the power source 16 or 17 is connected. The current flows through the switch SW2, the resistor 15, the switch SW1, and the terminal 13 from the wire 3, and no current flows through the detector 14. If the ball 3a is not connected to the pad electrode 6, no current flows through the wire 3, a current flows through the detector 14, and a wire connection failure signal is output from the detector 14.

지금, 전원(16, 17)으로부터 스위치(SW2)에 의해 선택된 전압을 Vr, 반도체칩(5)의 저항을 Rd(정확하게는 패드전극(6)으로부터 어스까지의 사이의 전기적 저항), 저항(15)을 Rs로 한다. 이 Rs는, Rd와 조합하여 반도체칩 (5)에 유입되는 전류(Id)의 량을 제한하는 저항(보호저항)이다. 또 검출기(14)에 입력되는 전압을 Vd, 이 Vd의 정의 전압 및 부의 전압의 임계값 전압을 Vt로 한다. 불착검출시에 흐르는 전류(Id) 및 검출기(14)에 입력되는 전압(Vd)은 [수 1] 및 [수 2]로 표시된다.Now, the voltage selected by the switch SW2 from the power supplies 16 and 17 is Vr, the resistance of the semiconductor chip 5 is Rd (exactly, the electrical resistance between the pad electrode 6 and the earth) and the resistance 15 Is set to Rs. This Rs is a resistance (protective resistance) for limiting the amount of current Id flowing into the semiconductor chip 5 in combination with Rd. The voltage input to the detector 14 is Vd, and the threshold voltage of the positive voltage and negative voltage of this Vd is Vt. The current Id flowing at the time of non-detection and the voltage Vd input to the detector 14 are represented by [number 1] and [number 2].

[수 1][1]

Id＝Vr/(Rs + Rd)Id = Vr / (Rs + Rd)

[수 2][Number 2]

Vd ＝ Rd × Id＝Rd×Vr/(Rs + Rd)Vd = Rd × Id = Rd × Vr / (Rs + Rd)

[수 2]로부터 명백한 바와 같이, Rd가 크게 될 수록 Vd는 Vr에 근접한다. 불찰 발생시에는 Rd＝∞로 생각되므로, Vd≒Vr로 된다. 도 8(a)는 Rd가 비교적 작은 경우로, 도 8(b)는 Rd가 비교적 큰 경우이다.As is apparent from Equation 2, the larger Rd is, the closer Vd is to Vr. At the time of non-occurrence, it is considered that Rd = ∞, and therefore Vd ≒ Vr. FIG. 8A illustrates a case where Rd is relatively small, and FIG. 8B illustrates a case where Rd is relatively large.

종래의 와이어본딩에 의한 불착검출방법에 있어서는, 반도체칩(5)의 전기적 저항(Rd)이 크게 될수록, Vr와 Vd 사이의 전위차가 좁게 되고, 임계값 전압(Vt)의 설정이 곤란하게 된다. 즉, 불착검출이 곤란하게 된다.In the conventional non-bonding detection method by wire bonding, the larger the electric resistance Rd of the semiconductor chip 5 becomes, the narrower the potential difference between Vr and Vd becomes, and the setting of the threshold voltage Vt becomes difficult. That is, non-detection becomes difficult.

또 와이어본딩에 있어서는, 패드전극(6)으로의 불착검출은, 도 7에 도시하는 바와 같이 와이어(3)를 리드(10a)에 접속할 때까지의 사이에 행하면 되므로, 와이어(3)를 풀어내는 시간(루핑시간)만큼 시간적으로 여유가 있다. 그러나, 도 4에 도시하는 범프본딩에 있어서는, 볼(3a)을 패드전극(6)에 접속후, 즉시 볼(3a)의 부착부분으로부터 와이어(3)을 절단하므로, 즉 루핑시간이 없으므로, 도 4(b)로부터 도 4(c) 사이에 겨우 캐필러리(2)가 이동하는 거리(50 ∼100㎛) 사이에 불착검출을 행하지 않으면 안되고, 시간적으로 여유가 없다.In wire bonding, the non-detection of the pad electrode 6 may be performed until the wire 3 is connected to the lead 10a as shown in FIG. 7, thereby releasing the wire 3. There is a time margin as time (looping time). However, in the bump bonding shown in Fig. 4, after the ball 3a is connected to the pad electrode 6, the wire 3 is immediately cut from the attachment portion of the ball 3a, i.e. there is no looping time. The non-detection must be performed between the distance (50-100 micrometers) which the capillary 2 moves only between 4 (b) and FIG. 4 (c), and there is no time.

한편, 도 6에 도시하는 검출기(14)의 입력에 접속된 회로에는 부유용량성분 (Cd)(도 1 참조)이 존재하기 때문에, 불착이 생긴 경우에도 검출전류(Id)가 흐르고 만다. 이때의 검출전류(Id)의 전류량은, 부유용량성분(Cd)에 전하를 충전하는 사이 전류가 일정시간 계속 흐르면서 서서히 0으로 되어간다. 종래는 그 후가 아니면 불착검출의 판정이 이 될 수 없었다. 따라서 범프본딩의 경우에는, 와이어본딩과 같은 와이어 풀어내기 시간이 존재하지 않는 분만큼, 시간적으로 제한이 엄하다.On the other hand, since the stray capacitance component Cd (see FIG. 1) exists in the circuit connected to the input of the detector 14 shown in FIG. 6, the detection current Id flows even when a failure occurs. At this time, the current amount of the detection current Id gradually becomes zero while the current continues to flow for a predetermined time while charging the floating capacitance component Cd. Conventionally, the determination of non-detection was not possible after that. Therefore, in the case of bump bonding, the time limit is severe as long as there is no wire unwinding time such as wire bonding.

본 발명의 과제는, 범프본딩에 있어서의 볼 불착을 단시간에 검출할 수 있는 불착검사방법 및 장치를 제공하는데 있다.An object of the present invention is to provide a non-adherence inspection method and apparatus capable of detecting ball non-adherence in bump bonding in a short time.

도 1은 본 발명의 범프본딩에 있어서의 불착검사장치의 한 실시형태를 도시하는 설명도,BRIEF DESCRIPTION OF THE DRAWINGS Explanatory drawing which shows one Embodiment of the non adhesion test apparatus in bump bonding of this invention.

도 2는 도 1의 컴퓨터의 구성을 도시하는 블록도,2 is a block diagram showing the configuration of the computer of FIG. 1;

도 3의 (a)는 정상으로 본딩된 경우의 타이밍도, (b)는 볼 불착이 발생한 경우의 타이밍도,(A) is a timing diagram in the case of normal bonding, (b) is a timing diagram in the case of a ball non-sticking,

도 4의 (a) 내지 (d)는 범프본딩공정을 도시하는 설명도,4 (a) to 4 (d) are explanatory diagrams showing a bump bonding step;

도 5의 (a), (b)는 볼 불착상태의 설명도,5 (a) and 5 (b) are explanatory diagrams of a ball non-stick state,

도 6은 종래의 와이어본딩에 있어서의 불착검사장치의 설명도,Fig. 6 is an explanatory diagram of a non-defective inspection device in conventional wire bonding;

도 7은 종래의 와이어본딩에 있어서의 불착검출 타이밍시의 본딩상태의 설명도, 및7 is an explanatory diagram of a bonding state at the time of non-detection timing in conventional wire bonding, and

도 8의 (a), (b)는 반도체칩의 저항의 대소에 의해 검출기에 입력되는 전압의 변화를 도시하는 설명도,8A and 8B are explanatory views showing changes in voltage input to the detector by the magnitude of the resistance of the semiconductor chip;

(부호의 설명)(Explanation of the sign)

1 : 클램퍼 2 : 캐필러리1: clamper 2: capillary

3 : 와이어 3a : 볼3: wire 3a: ball

4 : 방전전극 5 : 반도체 칩4 discharge electrode 5 semiconductor chip

6 : 패드전극 7 : 패드6 pad electrode 7 pad

10 : 리드프레임 10a : 리드10: lead frame 10a: lead

11 : 시료대 16, 17 : 전원11: sample stand 16, 17: power supply

20 : 컴퓨터 21 : 입력단자20: Computer 21: Input Terminal

22 : 소음제거회로 23 : 변위추출회로22: noise reduction circuit 23: displacement extraction circuit

24 : 비교회로 25 : 제어회로24: comparison circuit 25: control circuit

26 : 기준신호 발생회로 27 : 자기유지회로26: reference signal generating circuit 27: magnetic holding circuit

Vd : 입력전압 + V0, - V0 : 변위신호Vd: Input voltage + V0,-V0: Displacement signal

Vt : 임계값 전압 + Vth, - Vth : 임계값신호Vt: Threshold voltage + Vth,-Vth: Threshold signal

R : 클리어신호 S : 세팅신호R: Clear signal S: Setting signal

U : 이상검출신호U: Abnormal detection signal

상기 과제를 해결하기 위한 본 발명의 방법은, 와이어의 선단에 형성된 볼을 반도체칩에 접속한 후, 와이어를 볼의 부착부분에서 절단하여 반도체칩에 범프를 형성하는 범프본딩방법에 있어서, 볼을 반도체칩에 접속한 후, 와이어를 볼의 부착부분에서 절단하기까지의 기간에 와이어에 전압을 인가하고, 볼 불착의 유무에 의한 상기 기간중의 전압의 변화를 검출함으로써 볼 불착의 유무를 판정하는 것을 특징으로 한다.In the method of the present invention for solving the above problems, in the bump bonding method of forming a bump on a semiconductor chip by connecting the ball formed at the tip of the wire to the semiconductor chip, and then cutting the wire at the attachment portion of the ball. After connecting to the semiconductor chip, voltage is applied to the wire in the period from the attachment portion of the ball to the cutting, and the presence or absence of ball failure is determined by detecting a change in voltage during the period due to the presence or absence of ball failure. It is characterized by.

상기 과제를 해결하기 위한 본 발명의 제 1 장치는, 와이어의 선단에 형성된 볼을 반도체칩에 접속한 후, 와이어를 볼의 부착부분에서 절단하여 반도체칩에 범프를 형성하는 범프본딩장치에 있어서, 볼을 반도체칩에 접속한 후, 와이어를 볼의 부착부분에서 절단하기까지의 기간에, 와이어에 전압을 인가하는 전원과, 볼 불착의 유무에 의한 상기 기간중의 전압의 변화를 검출함으로써 볼 불착의 유무를 판정하는 컴퓨터를 구비한 것을 특징으로 한다.A first device of the present invention for solving the above problems is a bump bonding apparatus for connecting a ball formed at a tip of a wire to a semiconductor chip, and then cutting the wire at an attachment portion of the ball to form a bump on the semiconductor chip. After the ball is connected to the semiconductor chip, the ball failure is detected by detecting a power supply for applying a voltage to the wire and a change in voltage during the period due to the presence or absence of ball failure in the period until the wire is cut at the attachment portion of the ball. It is characterized by including a computer for determining the presence or absence of.

상기 과제를 해결하기 위한 본 발명의 제 2의 장치는, 상기 제 1의 장치에 있어서, 상기 컴퓨터는, 상기 기간중의 전위의 변화를 추출하여 변위신호로서 꺼내서 표시하는 변위추출회로와, 상기 변위신호와 기준신호를 비교하여, 변위신호의 절대값이 기준신호를 표시하는 임계값전압의 절대값보다 큰 경우에 세팅신호를 출력하는 비교회로와, 상기 기준신호를 상기 비교회로에 입력함과 동시에, 상기 세팅신호에 의해 이상검출신호를 출력하는 제어회로를 구비한 것을 특징으로 한다.In the first device of the present invention for solving the above problems, in the first device, the computer includes a displacement extraction circuit for extracting and displaying a change in potential during the period, as a displacement signal, and displaying the displacement. A comparison circuit for outputting a setting signal when the absolute value of the displacement signal is greater than the absolute value of the threshold voltage indicating the reference signal by comparing the signal with the reference signal, and simultaneously inputting the reference signal to the comparison circuit. And a control circuit for outputting the abnormal detection signal by the setting signal.

(실시형태)Embodiment

본 발명의 한 실시형태를 도 1 내지 도 5에 의해 설명한다. 또한, 도 6과 동일 또는 상당부재에는 동일한 부호를 붙여서 설명한다. 도 1은 반도체칩(5)이 예를 들면 은페이스트 등의 도전성 접착제로 리드프레임(10)에 고착된 공작물에 적용한 예를 표시한다. 반도체칩(5)이 고착된 리드프레임(10)은, 시료대(11)에 위치결정 고정되고, 반도체칩(5)의 패드전극(6)은, 반도체칩(6)의 내부저항(Rd), 리드프레임 (10)을 거쳐서 어스에 접속된다. 더구나 반도체칩(5)이 절연물로 이루어지는 기판 등에 고착되어 있는 경우에는, 반도체칩(5)은 미리 기판상에 설치된 배선패턴에 도통접속되고, 이 배선패턴을 통과하여 어스에 접속된다.An embodiment of the present invention will be described with reference to FIGS. 1 to 5. In addition, it demonstrates attaching | subjecting the same code | symbol to the member same or equivalent to FIG. 1 shows an example in which the semiconductor chip 5 is applied to a workpiece fixed to the lead frame 10 with a conductive adhesive such as silver paste, for example. The lead frame 10 to which the semiconductor chip 5 is fixed is fixed to the sample stage 11, and the pad electrode 6 of the semiconductor chip 5 has an internal resistance Rd of the semiconductor chip 6. The ground is connected to the earth via the lead frame 10. Moreover, when the semiconductor chip 5 is stuck to the board | substrate etc. which consist of an insulator, the semiconductor chip 5 is electrically connected to the wiring pattern previously provided on the board | substrate, and is connected to earth through this wiring pattern.

반도체칩(5)에 범프를 형성시키기 위한 와이어(3)는 스풀(12)에 감아돌려져 있으며, 일단은 캐필러리(2)에 끼워통하게 되고, 타단은 단자(13)에 접속되어 있다. 단자(13)는 스위치(SW1)의 공통접점(C)에 접속되며, 스위치(SW1)의 상시폐접점 (NO)은 어스되어 있다. 스위치(SW1)의 상시개접점(NO)는 저항(15)의 일단에 접속되어 있고, 저항(15)의 타단은 스위치(SW2)에 의해 2개의 전원(16, 17)에 선택적으로 접속된다. 2개의 전원(16, 17)을 설치한 것은, 반도체칩(5)의 패드전극(6)과 어스 사이에 다이오드특성이 있기 때문에, 반도체칩(5)에 의해서 극성(순차이송인지 또는 반대이송인지에 의한 극성)이 상이하기 때문에, 스위치(SW2)에 의해 극성을 반전시켜서 대응시킨다. 이상은, 도 6에 도시하는 종래예와 대략 동일한 구성이다. 또한, 도 1에 있어서, Cd는 컴퓨터(20)의 인력단자(21)에 접속된 회로의 부유용량성분을 표시한다.The wire 3 for forming bumps in the semiconductor chip 5 is wound around the spool 12, one end of which is inserted into the capillary 2, and the other end thereof is connected to the terminal 13. The terminal 13 is connected to the common contact C of the switch SW1, and the normally closed contact NO of the switch SW1 is earthed. The normally open contact NO of the switch SW1 is connected to one end of the resistor 15, and the other end of the resistor 15 is selectively connected to the two power supplies 16 and 17 by the switch SW2. The two power sources 16 and 17 are provided with a diode characteristic between the pad electrode 6 and the earth of the semiconductor chip 5, so that the semiconductor chip 5 is used for polarity (sequential or reverse transfer). Since the polarity by) is different, the polarity is reversed by the switch SW2 to correspond. The above is the structure substantially the same as the conventional example shown in FIG. 1, Cd indicates the stray capacitance component of the circuit connected to the attraction terminal 21 of the computer 20. In FIG.

상기 스위치(SW1)의 상시개방접점(NO)은 컴퓨터(20)의 인력단자(21)에 접속되어 있다. 또 스위치(SW1, SW2)에는, 도 3에 도시하는 타이밍에서 컴퓨터(20)에 의해 변환신호(SW1SEL,SW2SEL)가 출력된다.The normally open contact NO of the switch SW1 is connected to the attraction terminal 21 of the computer 20. In addition, the conversion signals SW1SEL and SW2SEL are output to the switches SW1 and SW2 by the computer 20 at the timing shown in FIG.

컴퓨터(20)는 도 2에 도시하는 바와 같은 구성으로 되어 있다. 입력단자(21)에 입력되는 신호에는, 배선경로나 와이어(3)로부터의 노이즈성분이 포함되어 있으므로, 노이즈제거회로(22)를 통과시켜 평활화하여 노이즈성분을 제거하고 다음의 변위추출회로(23)를 통과시켜 과도적인 전압의 변화를 추출하여 정부의 변위신호(＋VO, -VO)로서 꺼내어, 이 정부의 변위신호(＋VO, -VO)는 비교회로(24)에 입력된다.The computer 20 has a configuration as shown in FIG. Since the signal input to the input terminal 21 contains a noise path from the wiring path or the wire 3, it passes through the noise removing circuit 22 to smooth the noise component to remove the noise component, and the following displacement extraction circuit 23 ), The change in the transient voltage is extracted and taken out as the displacement signals (+ VO, -VO) of the government, and the displacement signals (+ VO, -VO) of the government are input to the comparison circuit 24.

제어회로(25)에는 미리 불착을 판정하기 위한 전압레벨을 표시하는 정부의 임계값이 교시되어 있고, 이 정부의 임계값은 기준신호 발생회로(26)에 입력된다. 기준신호 발생회로(26)는, 정부의 임계값을 근거로 하여 정의 임계값신호(＋Vth)와 부의 임계값신호(－Vth)를 생성하고, 이 정부의 임계값신호(＋Vth, －Vth)는 비교회로(24)에 입력된다. 비교회로(24)는 상기 정의 변위신호(＋VO)와 상기 정의 임계값신호(+Vth) 또는 상기 부의 변위신호(-VO)와 상기부의 임계값 신호(-Vth)를 비교하고, 상기 정의 변위신호(+VO)의 값이 상기 정의 임계값신호(+Vth)를 표시하는 임계값을 초과하는 경우, 또는 상기 부의 변위신호(－VO)의 값이 상기부의 임계값신호(－Vth)를 표시하는 임계값을 하회하는 경우, 즉 변위신호의 값이 정 또는 부의 임계값을 초과하는 경우에, 비교회로(24)는 세팅신호(S)를 출력한다. 이 세팅신호(S)가 자기유지회로(27)에 입력되면, 자기유지회로(27)는 불착판별신호 (Q)를 온 (ON)상태로 유지하고, 이 불착판별신호(Q)가 제어회로(25)에 입력된다. 제어회로 (25)에 불착판별신호(Q)가 입력되면, 이상검출신호(U)가 본딩장치에 출력된다.The control circuit 25 teaches in advance a threshold value indicating a voltage level for determining non-compliance, and this threshold value is input to the reference signal generation circuit 26. The reference signal generator 26 generates a positive threshold signal (+ Vth) and a negative threshold signal (−Vth) based on the threshold of the government, and the threshold signals (+ Vth, −Vth) of the government are generated. It is input to the comparison circuit 24. The comparison circuit 24 compares the positive displacement signal + VO with the positive threshold signal + Vth or the negative displacement signal -VO with the negative threshold signal -Vth, and the positive displacement signal with the positive displacement signal. When the value of (+ VO) exceeds the threshold indicating the positive threshold signal (+ Vth), or the value of the negative displacement signal (−VO) indicates the threshold signal (−Vth) of the part. When the threshold value is lowered, that is, when the value of the displacement signal exceeds the positive or negative threshold value, the comparison circuit 24 outputs the setting signal S. When this setting signal S is input to the magnetic holding circuit 27, the magnetic holding circuit 27 keeps the non-determination discrimination signal Q in an ON state, and this non-identifying discrimination signal Q is a control circuit. It is input to 25. When the failure determination signal Q is input to the control circuit 25, the abnormality detection signal U is output to the bonding apparatus.

다음에 작용에 관하여 설명한다. 도 1에 도시하는 스위치(SW2)는, 반도체칩(5)의 극성에 의해 전압레벨 및 그 극성이 결정되어 있으므로, 미리 ＋측 또는 －측의 어느 한쪽의 방향으로 변환되어 있다(컴퓨터(20)로부터의 변환신호 (SW2SEL)에 의해 그 극성이 결정된다). 스위치(SW1)는 미리 폐쇄접점(NC)측으로 되어 있다. 그래서 먼저, 도 4(a)에 도시하는 바와 같이, 클램퍼(1)가 폐쇄된 상태에서, 캐필러리(2)에 끼워통하게된 와이어(3)의 선단에 방전전극(4)으로부터의 방전에 의해 볼(3a)을 형성한다. 계속해서 클램퍼(1)가 열린다. 다음에 도 4(b)에 도시하는 바와 같이, 캐필러리(2)가 하강하여 볼(3a)을 반도체칩(5)의 패드전극(6) 표면에 눌러 붙인다.Next, the operation will be described. Since the voltage level and its polarity are determined by the polarity of the semiconductor chip 5, the switch SW2 shown in FIG. 1 is previously converted to either the + side or the-side (computer 20) Its polarity is determined by the conversion signal SW2SEL). The switch SW1 is previously set to the closed contact NC side. First, as shown in Fig. 4A, the discharge from the discharge electrode 4 is applied to the tip of the wire 3 inserted into the capillary 2 in a state where the clamper 1 is closed. The ball 3a is formed by this. The clamper 1 subsequently opens. Next, as shown in FIG. 4B, the capillary 2 descends and the ball 3a is pressed against the surface of the pad electrode 6 of the semiconductor chip 5.

그 후는 캐필러리(2)를 유지한 초음파혼(horn:경적)(도시 생략)에 의해 초음파를 인가하면서 캐필러리(2)로 볼(3a)을 가압하고, 볼(3a)을 가압변형시켜서 패드전극(6)에 볼(3a)을 접속한다. 이때, 컴퓨터(20)에서 변환신호(SW1SEL)이 출력하고, 스위치( SW1)는 개방접점(NO)측으로 변환되고(도 1, 도 3 참조), 볼(3a)이 정상으로 패드전극(6)에 접속되어 있으면, 상기 한 바와 같이 패드전극(6)은, 저항 (Rd), 리드프레임(10)을 거쳐서 어스되어 있으므로, 전원(16 또는 17)에서 스위치(SW2), 저항(15), 스위치(SW1), 단자(13)을 거쳐서 와이어(3)에 전류(Id)가 흐른다. 또 도 3(a)에 도시하는 바와 같이 불착판별신호(Q)가 온상태의 경우에는, 도 2에 도시하는 제어회로(25)로부터의 클리어신호(R)에 의해, 자기유지회로(27)의 불착판별신호(Q)를 오프(OFF) 상태로 복귀시킨다. 또한 도 3에는, 스위치(SW1)가 상시 폐쇄접점(NC)측으로부터 상시개방접점(NO)측으로 변환했을 때에 클리어신호 (R)가 출력하는 경우를 도시하고 있는데, 이 클리어신호(R)는, 다음의 세팅신호(S)가 출력되기 까지에 출력되면 된다.Thereafter, while applying an ultrasonic wave by an ultrasonic horn (not shown) holding the capillary 2, the ball 3a is pressed by the capillary 2, and the ball 3a is pressurized. The ball 3a is connected to the pad electrode 6 by being deformed. At this time, the conversion signal SW1SEL is output from the computer 20, the switch SW1 is converted to the open contact NO side (see FIGS. 1 and 3), and the ball 3a is normally turned on the pad electrode 6. As described above, since the pad electrode 6 is grounded through the resistor Rd and the lead frame 10 as described above, the switch SW2, the resistor 15, the switch at the power source 16 or 17 is connected. The current Id flows through the wire SW1 and the terminal 13 through the wire 3. In addition, as shown in Fig. 3A, when the non-arrival discrimination signal Q is in the ON state, the magnetic holding circuit 27 is driven by the clear signal R from the control circuit 25 shown in Fig. 2. The non-determining determination signal Q is returned to the OFF state. 3 shows a case where the clear signal R is output when the switch SW1 is switched from the normally closed contact NC side to the normally open contact NO side. It is enough to output until the next setting signal S is output.

다음에 도 4(c)에 도시하는 바와 같이, 캐필러리(2) 및 클램퍼(1)가 함께 상승하고, 다음의 볼(3a)을 형성하기위한 와이어(3)(테일)를 풀어내면서 어느 시점에서 클램퍼(1)가 폐쇄된다. 다시 캐필러리(2) 및 클램퍼(1)가 상승하고, 도 4(d)에 도시하는 바와 같이 와이어(3)가 볼(3a)의 부착부분에서 절단된다. 이것에 의해 범프(7)가 형성된다.Next, as shown in Fig. 4 (c), the capillary 2 and the clamper 1 are raised together, and while the wire 3 (tail) for forming the next ball 3a is unwound, At this point the clamper 1 is closed. The capillary 2 and the clamper 1 are raised again, and the wire 3 is cut at the attachment portion of the ball 3a as shown in Fig. 4 (d). As a result, the bumps 7 are formed.

상기한 동작에 있어서, 캐필러리(2)가 상승하여 클램퍼(1)가 폐쇄되기 까지, 비교회로(24)는 정의 변위신호(＋VO)와 정의 임계값신호(＋Vth), 또는 부의 변위신호(-VO)와 부의 임계값신호(-Vth)를 비교한다. 도 4(c)와 같이 정상인 경우에는 와이어(3)로부터 어스까지의 사이는 전기적 경로가 확립되므로, 와이어(3)에 전류(Id)가 흐른다. 와이어(3)에 전류(Id)가 흐르면 도 3(a)에 도시하는 바와 같이, 입력단자(21)에는 전류가 흐르지 않고, 즉 전압(Vd)이 발생하지 않고, 도 2 및 도 3(a)에 도시하는 비교회로(24)로부터 세팅신호(S)는 출력하지 않고, 볼(3a)의 불착이 발생하지 않은 것을 판단하게 된다.In the above operation, until the capillary 2 rises and the clamper 1 is closed, the comparison circuit 24 has a positive displacement signal + VO and a positive threshold signal + Vth or a negative displacement signal ( -VO) and the negative threshold signal (-Vth). In the normal case as shown in FIG. 4C, since an electrical path is established between the wire 3 and the earth, the current Id flows through the wire 3. When the current Id flows through the wire 3, as shown in Fig. 3A, no current flows through the input terminal 21, that is, no voltage Vd is generated, and Figs. The setting signal S is not outputted from the comparison circuit 24 shown in Fig. 2), and it is determined that the ball 3a does not occur.

캐필러리(2)가 상승하여 클램퍼(1)가 폐쇄되기까지에, 도 5(a)에 도시하는 바와 같이 볼(3a)의 불착이 발생한 경우에는, 와이어(3)로부터 어스까지의 사이는 전기적 경로가 확립되지 않으므로, 입력단자(21)의 전압값(Vd)은 부유용량성분(Cd)에 의해 전하가 축적되어 가므로, 도 3(b)에 도시하는 바와 같이 과도적인 전압의 변화를 표시한다. 입력단자(21)에 인가된 전압은, 도 2 및 도 3(b)에 도시하는 노이즈제거회로(22)에 의해 평활화되고, 변위추출회로(23)에 의해 과도적인 전압의 변화를 추출하여 변위신호(＋VO 또는 －VO)로서 비교회로(24)에 입력된다.When the capillary 2 rises and the clamper 1 closes, as shown in FIG. 5 (a), when the ball 3a fails, the wire 3 to the earth Since the electrical path is not established, the electric charge is accumulated by the stray capacitance component Cd at the voltage value Vd of the input terminal 21. Therefore, as shown in FIG. Display. The voltage applied to the input terminal 21 is smoothed by the noise removing circuit 22 shown in Figs. 2 and 3 (b), and the displacement extraction circuit 23 extracts the transient voltage change and displaces it. It is input to the comparison circuit 24 as a signal (+ VO or -VO).

그래서, 비교회로(24)는, 정의 변위신호(＋VO)의 값이 정의 임계값신호(＋Vth)를 표시하는 값을 초과하는 경우, 또는 부의 변위신호(－VO)의 값이 부의 임계값신호(－Vth)를 표시하는 값을 하회하는 경우, 즉 변위신호의 값이 정 또는 부의 임계값을 초월하는 경우, 세팅신호(S)를 자기유지회로(27)에 입력한다. 자기유지회로(27)는 불착판별신호(Q)를 온 상태로 유지하고, 이 불착판별신호 (Q)를 제어회로(25)에 출력한다. 제어회로(25)는 이상검출신호(U)를 출력하고, 이 이상검출신호(U)에 의해 본딩장치가 정지됨과 동시에, 램프, 경보 등에 의해 작업자에게 통보된다. 불착의 요인이 제거되면, 제어회로(25)는 자기유지회로(27)에 클리어신호 (R)를 출력하고, 불착판별신호(Q)를 오프 상태로 회복시킨다.Therefore, the comparison circuit 24 determines that the value of the positive displacement signal + VO exceeds the value indicating the positive threshold signal + Vth, or the value of the negative displacement signal -VO is a negative threshold signal ( When the value indicating −Vth) is less than that, i.e., when the value of the displacement signal exceeds the positive or negative threshold value, the setting signal S is input to the magnetic holding circuit 27. The magnetic holding circuit 27 keeps the non-determination discrimination signal Q on, and outputs the non-determination discrimination signal Q to the control circuit 25. The control circuit 25 outputs the abnormality detection signal U, and the bonding apparatus is stopped by this abnormality detection signal U, and the operator is notified by a lamp, an alarm or the like. When the cause of the failure is eliminated, the control circuit 25 outputs the clear signal R to the magnetic holding circuit 27, and restores the failure determination signal Q to the off state.

본 발명에 의하면, 볼을 반도체칩에 접속한 후, 와이어를 볼의 부착부분으로부터 절단하기까지의 기간에, 와이어에 전압을 인가하고, 볼 불착의 유무에 의한 상기 기간중의 전압의 변화를 검출함으로써, 볼 불착의 유무를 판정하므로, 범프본딩에 있어서의 볼 불착을 단시간에 검출할 수 있다.According to the present invention, after the ball is connected to the semiconductor chip, a voltage is applied to the wire in a period from the attachment portion of the ball to the cutting of the wire, and the change of the voltage during the period due to the absence of ball is detected. By determining the presence or absence of ball non-adherence, it is possible to detect ball non-contact in bump bonding in a short time.

Claims (3)

와이어의 선단에 형성된 볼을 반도체칩에 접속한 후, 와이어를 볼의 부착부분으로부터 절단하여 반도체칩에 범프를 형성하는 범프본딩방법에 있어서,In a bump bonding method in which a bump formed on a semiconductor chip is formed by connecting a ball formed at a tip of a wire to a semiconductor chip, and then cutting the wire from an attachment portion of the ball. 볼을 반도체칩에 접속한 후, 와이어를 볼의 부착부분으로부터 절단하기까지의 기간에, 와이어에 전압을 인가하고, 볼 불착의 유무에 의한 상기 기간중의 전압의 변화를 검출함으로써 볼 불착의 유무를 판정하는 것을 특징으로 하는 범프본딩에 있어서의 불착검사방법.After the ball is connected to the semiconductor chip, voltage is applied to the wire in the period from the attachment portion of the ball to cutting the wire, and the presence or absence of ball failure is detected by detecting a change in voltage during the period caused by the presence or absence of ball failure. A non-stick inspection method in bump bonding, characterized in that it is determined. 와이어의 선단에 형성된 볼을 반도체칩에 접속한 후, 와이어를 볼의 부착부분으로부터 절단하여 반도체칩에 범프를 형성하는 범프본딩장치에 있어서,In the bump bonding apparatus which connects the ball formed in the front-end | tip of a wire to a semiconductor chip, and cuts a wire from the attachment part of a ball, and forms a bump in a semiconductor chip, 볼을 반도체칩에 접속한 후, 와이어를 볼의 부착부분으로부터 절단하기까지의 기간에, 와이어에 전압을 인가하는 전원과, 볼 불착의 유무에 의한 상기 기간중의 전압의 변화를 검출함으로써 볼 불착의 유무를 판정하는 컴퓨터를 구비한 것을 특징으로 하는 범프본딩에 있어서의 불착검사장치.After the ball is connected to the semiconductor chip, the ball failure is detected by detecting a power supply for applying a voltage to the wire and a change in voltage during the period due to the presence or absence of ball failure in the period from the attachment portion of the ball to cutting the wire. A non-contact inspection apparatus in bump bonding, characterized by comprising a computer for determining the presence or absence. 제 2 항에 있어서, 상기 컴퓨터는, 상기 기간중의 전위의 변화를 추출해서 변위신호로서 꺼내는 변위추출회로와, 상기 변위신호와 기준신호를 비교하고, 변위신호의 값이 임계값신호를 표시하는 값을 초과한 경우에 세팅신호를 출력하는 비교회로와, 상기 기준신호를 상기 비교회로에 입력함과 동시에, 상기 세팅신호에 의해 이상검출신호를 출력하는 제어회로를 구비한 것을 특징으로 하는 범프본딩에 있어서의 불착검사장치.3. The computer program according to claim 2, wherein the computer compares the displacement extracting circuit which extracts the change in potential during the period and extracts it as a displacement signal, the displacement signal and the reference signal, and the value of the displacement signal indicates a threshold signal. And a comparison circuit for outputting a setting signal when the value is exceeded, and a control circuit for inputting the reference signal to the comparison circuit and outputting an abnormal detection signal according to the setting signal. Non-contact inspection apparatus in
KR1020000020225A 1999-04-21 2000-04-18 Bonding failure inspection method and apparatus for bump bonding KR20000071716A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP11113793A JP2000306940A (en) 1999-04-21 1999-04-21 Method and device for inspecting nonadhesion in bump bonding
JP99-113793 1999-04-21

Publications (1)

Publication Number Publication Date
KR20000071716A true KR20000071716A (en) 2000-11-25

Family

ID=14621239

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020000020225A KR20000071716A (en) 1999-04-21 2000-04-18 Bonding failure inspection method and apparatus for bump bonding

Country Status (3)

Country Link
JP (1) JP2000306940A (en)
KR (1) KR20000071716A (en)
TW (1) TW454279B (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101326098B1 (en) * 2013-01-21 2013-11-06 주식회사 아이비에스 Method for inspecting wire bonding

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4106008B2 (en) 2003-09-22 2008-06-25 株式会社新川 Wire bonding method and apparatus
JP4266369B2 (en) 2005-02-24 2009-05-20 株式会社新川 Wire bonding method
JP5700482B2 (en) 2012-11-16 2015-04-15 株式会社新川 Wire bonding apparatus and semiconductor device manufacturing method
JP5426000B2 (en) 2012-11-16 2014-02-26 株式会社新川 Wire bonding apparatus and wire bonding method
CN104813457B (en) 2012-11-16 2017-08-04 株式会社新川 Throwing device and routing method
SG11201811528TA (en) * 2016-03-25 2019-01-30 Shinkawa Kk Wire bonding apparatus, circuit for wire bonding apparatus, and method for manufacturing semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101326098B1 (en) * 2013-01-21 2013-11-06 주식회사 아이비에스 Method for inspecting wire bonding

Also Published As

Publication number Publication date
TW454279B (en) 2001-09-11
JP2000306940A (en) 2000-11-02

Similar Documents

Publication Publication Date Title
US6247629B1 (en) Wire bond monitoring system for layered packages
EP1182460B1 (en) Fritting inspection method and apparatus
KR101596249B1 (en) Wire bonding apparatus and method for producing semiconductor device
KR101672510B1 (en) Wire bonding device and wire bonding method
JPH0141031B2 (en)
KR20000071716A (en) Bonding failure inspection method and apparatus for bump bonding
CN106158680A (en) A kind of chip-packaging structure detecting system
KR100730046B1 (en) Bonding apparatus
US5058797A (en) Detection method for wire bonding failures
US6529011B1 (en) Method and apparatus for inspecting electronic components
EP0575061B1 (en) Method of testing continuity of a connection between an IC and a PCB
US6039234A (en) Missing wire detector
US6568581B2 (en) Detection of wire bonding failures
JPH08201425A (en) Semiconductor acceleration detector
JPH0133941B2 (en)
CN109152196A (en) A kind of fingerprint recognition mould group installation method and fingerprint recognition mould group
JPH08264586A (en) Judgement method of semiconductor device state and state judging device
JP3537083B2 (en) Wire bonding equipment
JPH11243119A (en) Method and device for wire bonding
JPH11176868A (en) Wire bonding device
JPH11191564A (en) Bump bonding method and equipment
JPS6384132A (en) Method and apparatus for inspecting wire bonding
US6246073B1 (en) Semiconductor device and method for producing the same
JP2004119640A (en) Method and device for wire bonding
KR850002945Y1 (en) Semiconductor connect line

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E601 Decision to refuse application