KR970019662A

KR970019662A - Interface circuit between input buffer and variable length decoder in amplifier decoder and interfacing method

Info

Publication number: KR970019662A
Application number: KR1019950033222A
Authority: KR
Inventors: 심대윤
Original assignee: 김광호; 삼성전자 주식회사
Priority date: 1995-09-30
Filing date: 1995-09-30
Publication date: 1997-04-30
Also published as: KR0171850B1

Abstract

1. 청구범위에 기재된 발명이 속한 기술분야1. TECHNICAL FIELD OF THE INVENTION

엠펙디코더의 입력버퍼와 가변장디코더에 관한 것이다.It relates to an input decoder of an MPEG decoder and a variable length decoder.

2. 발명이 해결하려고 하는 기술적 과제2. The technical problem to be solved by the invention

엠펙디코더의 입력버퍼에 라이트되어 있는 데이터가 리드요구될 시 즉시 리드되어 가변장디코더로 제공되도록 한다.When the data written to the input decoder of the MPEG decoder is requested to be read, it is immediately read to provide the variable length decoder.

3. 발명의 해결방법의 요지3. Summary of Solution to Invention

본 발명에 따라 MPEG디코더의 입력버퍼와 VLD를 인터페이싱하는 회로는, 리세트신호가 입력될 시 상기 입력버퍼를 초기화하고 리드요청신호를 발생하여 상기 입력버퍼의 적정 레벨에 입력데이타가 라이트되도록 하고, 상기 입력버퍼에 입력데이타를 라이트한 후에는 첫 번째로 라이트된 입력 데이터를 리드하여 상기 가변장디코더로 출력하는 리세트루틴 처리수단과, 새로운신호를 로드하기 위한 신호가 발생될 시 상기 리세트루틴 처리수단에서 리드된 첫 번째 입력데이타 이후의 일련의 입력데이타들을 상기 로드신호가 발생됨과 동시에 한 비트씩 리드하여 상기 가변장디코더로 출력하는 리세트루틴 처리수단으로 구성함을 특징으로 한다.According to the present invention, a circuit for interfacing an input buffer and a VLD of an MPEG decoder, when a reset signal is input, initializes the input buffer and generates a read request signal so that input data is written at an appropriate level of the input buffer. After the input data is written to the input buffer, reset routine processing means for reading the first written input data and outputting the first written input data to the variable length decoder and the reset routine when a signal for loading a new signal is generated. A series of input data subsequent to the first input data read by the processing means is configured as a reset routine processing means for reading the bit signal at the same time as the load signal is generated and outputting it to the variable-length decoder.

4. 발명의 중요한 용도4. Important uses of the invention

엠펙디코더MPEG Decoder

Description

Interface circuit between input buffer and variable length decoder in amplifier decoder and interfacing method

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 본 발명에 따른 인터페이스회로가 입력버퍼와 가변장디코더의 사이에 연결됨을 나타내는 도면1 is a diagram showing that an interface circuit according to the present invention is connected between an input buffer and a variable length decoder.

제2도는 본 발명에 따른 인터페이스회로의 구성을 보다 상세히 나타내는 도면2 is a view showing in more detail the configuration of the interface circuit according to the present invention

Claims

A circuit for interfacing data transmitted between an input decoder of an MPEG decoder and a variable long decoder, wherein when a reset signal is input, the input buffer is initialized and a read request signal is generated to input data at an appropriate level of the input buffer. After writing the input data to the input buffer, reset routine processing means for reading the first written input data and outputting to the variable-length decoder, and a signal for loading a new signal will be generated. A series of input data subsequent to the first input data read by the reset routine processing means is configured as a reset routine processing means for reading out one bit at the same time as the load signal is generated and outputting the data to the variable length decoder. Interface circuit

The method of claim 1, wherein the reset routine processing means reads out the input data written to the input butter one bit at a time point at which the load signal is generated, and outputs the data to the variable length decoder before the input butter is preset. When the level is empty, the interface circuit further generates a signal requesting to read the input data written to the input buffer and outputs the signal to the variable length decoder.

The variable length decoder according to claim 2, wherein the reset routine processing means writes data written to the input buffer when a read accept signal in response to the request signal is not input within a predetermined time from the variable length decoder. The interface circuit further characterized in that the operation to block the transmission to

A circuit for interfacing data transmitted between an input decoder of an MPEG decoder and a variable long decoder, the circuit comprising: initializing the input buffer in response to a reset signal being input, writing a series of input data to the input buffer, and then inputting the next input. A first step of requesting the variable length decoder to read the written series of input data so that data is written; and even if a predetermined time has elapsed after the read request is made in the first step, the variable length decoder And a second process of holding an operation of transmitting data to the variable length decoder when a read accept signal is not input.

5. The method of claim 4, wherein a third process of transmitting a series of input data to the variable length decoder when a read accept signal is input from the variable length decoder after a preset time elapses after the read request in the first process. Interface method characterized in that it further comprises

※ Note: The disclosure is based on the initial application.