KR940017827A

KR940017827A - Recording speed control device and its operation method

Info

Publication number: KR940017827A
Application number: KR1019920027367A
Authority: KR
Inventors: 이승환; 이영범
Original assignee: 김주용; 현대전자산업 주식회사
Priority date: 1992-12-31
Filing date: 1992-12-31
Publication date: 1994-07-27
Also published as: KR100275118B1

Abstract

본 발명은 화상 데이타를 기록하기 위한 장치에서 기록 속도 제어를 하는데 사용하며 부호 버퍼를 이용하여 안정된 속도 제어를 하는 것에 관한 것으로, 특히 G3 팩스나 G4팩스에서 처럼 화상신호를 압축해서 전송하는 시스템에서 매 라인마다의 기록 속도를 제어하여 안정된 기록부 인쇄를 위하여 부호버퍼를 이용한 기록 속도 제어장치 및 그 운용 방법에 관한 것으로, 부호 데이타를 관리하는 중앙제어장치(31), 상기 중앙제어 장치(31)에 연결되어 기록부를 관장하는 마이크로 프로세서(33), 상기 중앙제어 장치(31)와 마이크로 프로세서(33)에 연결되어 동시에 사용되는 공용 메모리(32), 상기 마이크로 프로세서(33)와 상기 공용 메모리(32)에 연결되어 부호화된 화상데이타를 저장하는 부호 버퍼(35), 상기 마이로 프로세서(33)에 연결되어 상기 부호 버퍼(35)에서 데이타를 읽어 복호화하는 디코더(34), 및 상기 디코더(34)에 연결되어 복호화된 화상 데이타를 인쇄하는 기록장치(6)를 구비한다.BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to stable speed control using a code buffer in a device for recording image data, and particularly in a system for compressing and transmitting image signals such as in G3 fax or G4 fax. The present invention relates to a recording speed control device using a code buffer and a method of operating the same, in order to control the recording speed for each line and to print a stable recording unit, and to the central control device 31 and the central control device 31 for managing code data. To the microprocessor 33, the central control unit 31, and the microprocessor 33, which are used at the same time to manage the recording unit, to the microprocessor 33 and the common memory 32. A code buffer 35 for storing encoded image data, and connected to the miro processor 33 to the code buffer 35. A decoder 34 for reading and decoding the data, and a recording device 6 connected to the decoder 34 for printing the decoded image data.

Description

Recording speed control device and its operation method

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제3도는 본 발명에 따른 기록 속도 제어 장치 블럭구성도, 제4도는 본 발명에 따른 제어 방법의 흐름도.3 is a block diagram of a recording speed control apparatus according to the present invention, and FIG. 4 is a flowchart of a control method according to the present invention.

Claims

A central control unit 31 for managing code data, a microprocessor 33 connected to the central control unit 31 to manage a recording unit, connected to the central control unit 31 and a microprocessor 33 for simultaneous use A common memory 32, a code buffer 35 connected to the microprocessor 33 and the common memory 32 to store encoded image data, and a code buffer 35 connected to the microprocessor 33. And a recording device (6) connected to the decoder (34) for reading and decoding the data, and for printing the decoded image data.

A control method of a recording speed control device including a central control device (31), a microprocessor (33), a common memory (32), a code buffer (35), a decoder (34), and a recording device (6); A first step (40, 41) of checking whether or not to start processing by checking the amount of data determined to start the initial processing, and a second step of determining whether the amount of data in the code buffer is equal to the current amount of data after performing the first step. (42) In the third step (43,48) of determining the increase or decrease of the data amount of the code buffer after performing the second step, and whether the speed of the recording unit reaches the minimum speed (Vn) after performing the third step. Fourth step (44,45) of judging, after performing the third step, fifth step (46,47) of judging whether the speed of the recording unit reaches the maximum speed (VO), the third, fourth, fifth step And a sixth step (49 to 52) for determining whether a signal for notifying the end of the page has been input after the execution.

※ Note: The disclosure is based on the initial application.