KR910003526A - Image processing device - Google Patents

Abstract

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Description

Image processing device

Since this is an open matter, no full text was included.

1 is a block diagram schematically showing the configuration of an image processing apparatus according to an embodiment of the present invention;

FIG. 2 is a block diagram specifically showing a connection relationship between a CODEC circuit and an expansion / reduction circuit among the blocks of the image processing apparatus shown in FIG. 1;

3 is a flowchart illustrating the operation of the CPU during FIG.

Claims (9)

A storage means 20 in which a plurality of images are encoded and stored, a reading means 22 for reading out an image stored in the storage means 20, and an image read out by the reading means 22, And a processing means (14) for performing linear density conversion processing on the encoded image. A storage unit 20 in which a plurality of images are encoded and stored, a reading unit 22 for reading out the image stored in the storage unit 20, and a decoding for decoding the image read out by the reading unit 22. A processing means 14 having a means 50 and a converting means 46 for performing linear density conversion on the decoded image, and a bus 56 connecting the decoding means 50 and the converting means 46. An image processing apparatus, characterized in that provided with. Optical storage means 20 in which a plurality of images are encoded and stored, reading means 22 for reading out the image stored in the optical storage means 20, and decoding the image read out by the reading means 22. A processing means 14 having a decoding means 50, and a converting means 46 for linearly density converting the decoded image, and a bus 56 connecting the decoding means 50 and the converting means 46. And a page memory (40) for storing an image converted by said converting means (46). A plurality of images are encoded and stored in the first storage means 40a stored as image data, the system control bus 30 connected to the first storage means 40a, and the first storage means 40a. Reading means 10 for reading image data, decoding means 50 for decoding the image read out by the reading means 10, and an internal bus to which image data decoded by the decoding means 50 is sent out; 56, a line density converting means 46 connected to the internal bus 56 to convert a predetermined linear density of the decoded image data, an image bus 32 to which the linear density converted image data is sent out, and this image bus And second storage means (40) connected to (32) to store the linearly density-converted image data. An image processing apparatus according to claim 4, wherein said first storage means (40a) is constituted by a buffer memory having a FIFO configuration. An image processing apparatus according to claim 4, wherein said reading means (10) comprises a CPU (34) connected to said system control bus (30). 5. The decoding circuit (50) according to claim 4, wherein said decoding means (50) comprises a codec circuit having a code data input / output stage and an image data input / output stage, and a first gate (62) between said system control bus (30) and said code data input / output stage. Is connected, and a second gate (64) is connected between the image data input / output terminal and the internal bus (56). 8. An image processing apparatus according to claim 7, wherein a third gate (66) is connected between said flower reduction circuit (46) and an internal bus (56). An image processing apparatus according to claim 4, wherein said second storage means (40) is constituted by a page memory. ※ Note: The disclosure is based on the initial application.