KR970018396A - Formation method of multilayer wiring - Google Patents

Formation method of multilayer wiring Download PDF

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Publication number
KR970018396A
KR970018396A KR1019950029506A KR19950029506A KR970018396A KR 970018396 A KR970018396 A KR 970018396A KR 1019950029506 A KR1019950029506 A KR 1019950029506A KR 19950029506 A KR19950029506 A KR 19950029506A KR 970018396 A KR970018396 A KR 970018396A
Authority
KR
South Korea
Prior art keywords
etching process
lower wiring
wiring
etching
metal layer
Prior art date
Application number
KR1019950029506A
Other languages
Korean (ko)
Inventor
이기영
Original Assignee
김광호
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김광호, 삼성전자 주식회사 filed Critical 김광호
Priority to KR1019950029506A priority Critical patent/KR970018396A/en
Publication of KR970018396A publication Critical patent/KR970018396A/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226—Via connections in a multilevel interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76885—By forming conductive members before deposition of protective insulating material, e.g. pillars, studs

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

반도체 소자의 다층 배선 형성 방법에 관한 것으로서 더욱 상세하게는 하부 배선층과 상부 배선을 연결하는 비아-콘택트(VIA-contact)를 하부 배선의 형성시 동시에 형성시키는 방법이 개시된다. 본 발명에 따른 다층 배선의 형성 방법은 하부 배선용의 금속층을 적어도 비아 콘택트의 높이만큼 도포하는 공정; 상기 하부 배선용금속층을 비아 콘택트가 위치할 영역을 제외하고 하부 배선의 높이까지 식각하는 제1식각공정; 상기 제1식각공정의 결과물을 하부 배선 마스크를 사용하여 식각하여 하부 배선 패턴을 형성하는 제2식각공정; 상기 제2식각공정의 결과물에 하부 배선층과 상부 배선층을 전기적로 격리하기 위한 층간 절연물을 상기 비아 홀이 위치할 영역의 도체층보다 높게 도포하는 공정; 상기 층간 절연물을 상기 비아 홀이 위치할 영역의 금속층이 드러나도록 식각하는 제3식각공정; 및 상기 제3식각공정의 결과물에 상부 배선용의 금속층을 도포하는 공정을 포함함을 특징으로 한다.The present invention relates to a method for forming a multilayer wiring of a semiconductor device, and more particularly, a method of simultaneously forming a VIA contact connecting a lower wiring layer and an upper wiring to a lower wiring. A method of forming a multilayer wiring according to the present invention includes the steps of applying a metal layer for lower wiring by at least the height of a via contact; A first etching process of etching the lower wiring metal layer to a height of the lower wiring except for a region where a via contact is to be located; A second etching process of etching the resultant of the first etching process using a lower wiring mask to form a lower wiring pattern; Applying an interlayer insulator for electrically isolating the lower wiring layer and the upper wiring layer to the resultant of the second etching process higher than the conductor layer in the region where the via hole is to be located; A third etching process of etching the interlayer insulator so that the metal layer of the region where the via hole is to be exposed is exposed; And applying a metal layer for upper wiring to the resultant of the third etching process.

Description

다층배선의 형성 방법Formation method of multilayer wiring

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1E도 내지 제1G도는 본 발명의 다층 배선 형성 방법을 순차적으로 보이는 단면도이다.1E to 1G are cross-sectional views sequentially showing the method for forming a multilayer wiring of the present invention.

Claims (2)

반도체 소자의 다층 배선을 형성하는 방법에 있어서, 하부 배선용의 금속층을 적어도 비하 콘텍트의 높이 만큼 도포 하는 공정; 상기 하무 배선용 금속층을 비아 콘택트가 위치할 영역을 제외하고 하부 배선의 높이까지 식각하는 제1식각공정; 상기 제1식각공정의 결과물을 하부 배선 마스크를 사용하여 식각하여 하부 배선 패턴을 형성하는 제2식각공정; 상기 제2식각공정의 결과물에 하부 배선층과 상부 배선층을 전기적으로 결리하기 위한 층간 절연물을 상기 비아 홀이 위치할 영역의 도체층보다 높게 도포하는 공정; 상기 층간 절연물을 상기 비아 홀이 위치할 영역의 금속층이 드러나도록 식각하는 제3식각공정; 및 상기 제3식각공정의 결과물에 상부 배선용의 금속층을 도포하는 공정을 포함하는 다층 배선의 형성 방법.CLAIMS What is claimed is: 1. A method of forming a multilayer wiring of a semiconductor device, comprising: applying a metal layer for lower wiring by at least the height of a non-contacting contact; A first etching process of etching the lower wiring metal layer to a height of a lower wiring except for a region where a via contact is to be located; A second etching process of etching the resultant of the first etching process using a lower wiring mask to form a lower wiring pattern; Applying an interlayer insulator for electrically isolating the lower wiring layer and the upper wiring layer to the resultant of the second etching process than the conductor layer in the region where the via hole is to be located; A third etching process of etching the interlayer insulator so that the metal layer of the region where the via hole is to be exposed is exposed; And applying a metal layer for upper wiring to the resultant of the third etching process. 제1항에 있어서, 상기 제1식각공정의 다음에 상기 제1식각공정의 결과물 상에 TiN을 도포하는 공정을 더 구비함을 특징으로 하는 다층 배선의 형성 방법.The method of claim 1, further comprising: applying TiN on the resultant of the first etching process after the first etching process.
KR1019950029506A 1995-09-11 1995-09-11 Formation method of multilayer wiring KR970018396A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950029506A KR970018396A (en) 1995-09-11 1995-09-11 Formation method of multilayer wiring

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950029506A KR970018396A (en) 1995-09-11 1995-09-11 Formation method of multilayer wiring

Publications (1)

Publication Number Publication Date
KR970018396A true KR970018396A (en) 1997-04-30

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KR1019950029506A KR970018396A (en) 1995-09-11 1995-09-11 Formation method of multilayer wiring

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100593126B1 (en) * 1999-12-29 2006-06-26 주식회사 하이닉스반도체 Method of forming a metal wiring in a semiconductor device
WO2018080125A1 (en) * 2016-10-24 2018-05-03 주식회사 엘지화학 Insulation layer manufacturing method and multilayer printed circuit board manufacturing method
KR20180044816A (en) * 2016-10-24 2018-05-03 주식회사 엘지화학 Method for manufacturing insulating film and multilayered printed circuit board
KR20180053228A (en) * 2016-11-11 2018-05-21 주식회사 엘지화학 Method for manufacturing insulating film and multilayered printed circuit board

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100593126B1 (en) * 1999-12-29 2006-06-26 주식회사 하이닉스반도체 Method of forming a metal wiring in a semiconductor device
WO2018080125A1 (en) * 2016-10-24 2018-05-03 주식회사 엘지화학 Insulation layer manufacturing method and multilayer printed circuit board manufacturing method
KR20180044816A (en) * 2016-10-24 2018-05-03 주식회사 엘지화학 Method for manufacturing insulating film and multilayered printed circuit board
CN109156084A (en) * 2016-10-24 2019-01-04 株式会社Lg化学 Method for manufacturing insulating layer and multilayer board
TWI672985B (en) * 2016-10-24 2019-09-21 南韓商Ｌｇ化學股份有限公司 Method for manufacturing insulating layer and multilayered printed circuit board
CN109156084B (en) * 2016-10-24 2021-04-30 株式会社Lg化学 Method for manufacturing insulating layer and multilayer printed circuit board
KR20180053228A (en) * 2016-11-11 2018-05-21 주식회사 엘지화학 Method for manufacturing insulating film and multilayered printed circuit board

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