KR950006986A - Method of forming via contact for metal wiring connection of semiconductor device - Google Patents

Method of forming via contact for metal wiring connection of semiconductor device Download PDF

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Publication number
KR950006986A
KR950006986A KR1019930015863A KR930015863A KR950006986A KR 950006986 A KR950006986 A KR 950006986A KR 1019930015863 A KR1019930015863 A KR 1019930015863A KR 930015863 A KR930015863 A KR 930015863A KR 950006986 A KR950006986 A KR 950006986A
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KR
South Korea
Prior art keywords
via contact
layer
forming
semiconductor device
metal wiring
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Application number
KR1019930015863A
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Korean (ko)
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KR960015493B1 (en
Inventor
최경근
Original Assignee
김주용
현대전자산업 주식회사
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Priority to KR1019930015863A priority Critical patent/KR960015493B1/en
Publication of KR950006986A publication Critical patent/KR950006986A/en
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Publication of KR960015493B1 publication Critical patent/KR960015493B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

본 발명은 개방된 비아홀의 AI층 상에서만 AI-Ti합금층을 형성시킨 후, 선택 CVD텅스텐의 성장으로 개방된 비아홀을 충진하여 비아 콘택이 형성되도록 한 반도체 소자의 금속 배선 연결용 비아콘택 형성방법에 관해 기술된다.According to the present invention, after forming an AI-Ti alloy layer only on an AI layer of an open via hole, a via contact is formed in a semiconductor device for forming a via contact by filling an open via hole by growth of selective CVD tungsten. Is described.

Description

반도체 소자의 금속배선 연결용 비아콘택 형성방법Method of forming via contact for metal wiring connection of semiconductor device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도 내지 제4도는 본 발명에 따른 반도체 소자의 금속배선 연결용 비아콘택 형성단계를 나타내는 단면도.1 to 4 are cross-sectional views showing a via contact forming step for connecting metal wirings of a semiconductor device according to the present invention.

Claims (3)

반도체 소자의 금속배선 연결용 비아콘택 형성방법에 있어서, 하층 절연부로 이루어진 기판(1)상에 제1 및 제2도전층(2A 및 2B)을 형성하고, 전체구조상부에 제1,2 및 3절연층(3,4 및 5)을 형성한 다음, 상기 제1 및 제2도전층(2B 및 2B)상부의 제1,2 및 3절연층(3,4,5)을 소정폭으로 식각하여, 제1 및 제2비아콘택홀(10 및 11)을 형성하는 단계와, 상기 단계로부터 전체 구조상부에 Ti층(6)을 형성하고 열처리하여 상기 제1 및 제2도전층 상부에만 AI합금층이 형성되도록 하고, 상기 제3절연층(5)상부 및 상기 제1 및 제2비아콘택홀(10 및 11)측벽의 Ti층(6)을 제거하는 단계와, 상기 단계로부터 상기 A합금층 상부에 텅스텐을 성장시킨 후, 제3도전층(9)을 형성하는 단계로 이루어지는 것을 특징으로 하는 반도체 소자의 금속배선 연결용 비아콘택 형성방법.In the method for forming a via contact for connecting a metal wire of a semiconductor device, the first and second conductive layers 2A and 2B are formed on a substrate 1 formed of a lower insulating portion, and the first, second and third portions are formed on the entire structure. After the insulating layers 3, 4 and 5 are formed, the first, second and third insulating layers 3, 4 and 5 on the first and second conductive layers 2B and 2B are etched to a predetermined width. Forming the first and second via contact holes 10 and 11, and forming a Ti layer 6 on the entire structure from the step and heat-treating the AI alloy layer only on the first and second conductive layers. And the Ti layer 6 on the sidewalls of the third insulating layer 5 and the sidewalls of the first and second via contact holes 10 and 11, and the upper portion of the A alloy layer from the step. And forming a third conductive layer (9) after the tungsten is grown on the via. 제1항에 있어서, 상기 Ti층(6)은 희석된 H2O2에 의한 습식식각 공정에 의해 제거되는 것을 특징으로 하는 반도체 소자의 금속배선 연결용 비아콘택 형성방법.The method of claim 1, wherein the Ti layer (6) is removed by a wet etching process using dilute H 2 O 2 . 제1항에 있어서, 상기 제1 및 제2비아콘택홀(2A 및 2B) 형성 후, 상기 제1 및 제2도전체 상에 직접 AI 합금층을 형성하는 것을 특징으로 하는 반도체 소자의 금속배선 연결용 비아콘택 형성방법.The metal wire connection of the semiconductor device according to claim 1, wherein after forming the first and second via contact holes 2A and 2B, an AI alloy layer is formed directly on the first and second conductors. Via contact formation method for. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019930015863A 1993-08-17 1993-08-17 Via contact forming method KR960015493B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019930015863A KR960015493B1 (en) 1993-08-17 1993-08-17 Via contact forming method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019930015863A KR960015493B1 (en) 1993-08-17 1993-08-17 Via contact forming method

Publications (2)

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KR950006986A true KR950006986A (en) 1995-03-21
KR960015493B1 KR960015493B1 (en) 1996-11-14

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KR1019930015863A KR960015493B1 (en) 1993-08-17 1993-08-17 Via contact forming method

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100440467B1 (en) * 2001-11-12 2004-07-14 아남반도체 주식회사 Formation method of stacking structure of metal line in semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100440467B1 (en) * 2001-11-12 2004-07-14 아남반도체 주식회사 Formation method of stacking structure of metal line in semiconductor device

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Publication number Publication date
KR960015493B1 (en) 1996-11-14

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