KR970003495A

KR970003495A - Via contact method in the manufacture of semiconductor devices

Info

Publication number: KR970003495A
Application number: KR1019950017569A
Authority: KR
Inventors: 오진성; 김문환; 엄용택
Original assignee: 김주용; 현대전자산업 주식회사
Priority date: 1995-06-26
Filing date: 1995-06-26
Publication date: 1997-01-28

Abstract

본 발명은 반도체 소자 제조시 소정 하부층과의 절연을 위해 제1절연층(1)을 형성하는 단계를 포함하는 콘택 방법에 있어서, 상기 제1절연층 상에 제1전도층(2)을 형성한 후, 콘택홀로 예정된 부위(2a)를 제외한 부위의 상기 제1전도층을 일부 깊이 식각하는 제1단계; 상기 제1도전층을 패터닝하여 예정된 패턴을 형성한 후, 전체 구조 상부에 제2절연층(3)을 형성하는 제2단계; 콘택홀로 예정된 부위의 상기 제2절연층을 제거하는 제3단계; 및 전체구조 상에 제2전도층(5)을 형성하는 제4단계를 포함하는 것을 특징으로 하는 콘택 방법에 관한 것으로, 수평방향으로의 식각없이 스텝 커버리지를 향상시킬 수 있어 집적도 및 제소 수율을 향상시킬 수 있도록 한 것이다.The present invention provides a contact method comprising forming a first insulating layer (1) to insulate a predetermined lower layer in the manufacture of a semiconductor device, the first conductive layer (2) formed on the first insulating layer Thereafter, a first step of partially etching the first conductive layer of the portion except for the portion 2a scheduled as the contact hole; A second step of forming a predetermined pattern by patterning the first conductive layer, and then forming a second insulating layer 3 over the entire structure; A third step of removing the second insulating layer in a predetermined portion of the contact hole; And a fourth step of forming a second conductive layer (5) on the overall structure, wherein the step coverage can be improved without etching in the horizontal direction, thereby improving the degree of integration and the yield. It was made to be possible.

Description

Via contact method in the manufacture of semiconductor devices

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1A도 내지 제1E도는 본 발명에 따른 비아 콘택 과정도.1A-1E are via contact process diagrams in accordance with the present invention.

Claims

A contact method comprising forming a first insulating layer to insulate a predetermined lower layer when manufacturing a semiconductor device, wherein after forming the first conductive layer on the upper first insulating layer, except for a portion that is intended as a contact hole A first step of partially etching the first conductive layer of the substrate; Forming a predetermined pattern by patterning the first conductive layer, and then forming a second insulating layer over the entire structure; A third step of removing the second insulating layer in a predetermined portion of the contact hole; And a fourth step of forming a second conductive layer on the entire structure.

※ Note: The disclosure is based on the initial application.