KR970018288A - Manufacturing method of array passive components for wire bonding - Google Patents

Manufacturing method of array passive components for wire bonding Download PDF

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Publication number
KR970018288A
KR970018288A KR1019950028919A KR19950028919A KR970018288A KR 970018288 A KR970018288 A KR 970018288A KR 1019950028919 A KR1019950028919 A KR 1019950028919A KR 19950028919 A KR19950028919 A KR 19950028919A KR 970018288 A KR970018288 A KR 970018288A
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KR
South Korea
Prior art keywords
array
wire bonding
forming
photoresist
resistor
Prior art date
Application number
KR1019950028919A
Other languages
Korean (ko)
Other versions
KR0167009B1 (en
Inventor
이충국
Original Assignee
우덕창
쌍용양회공업 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 우덕창, 쌍용양회공업 주식회사 filed Critical 우덕창
Priority to KR1019950028919A priority Critical patent/KR0167009B1/en
Publication of KR970018288A publication Critical patent/KR970018288A/en
Application granted granted Critical
Publication of KR0167009B1 publication Critical patent/KR0167009B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Parts Printed On Printed Circuit Boards (AREA)
  • Apparatuses And Processes For Manufacturing Resistors (AREA)

Abstract

본 발명은 와이어본딩용 어레이형 수동 칩부품, 즉 저항기, 캐패시터, 인덕터의 어레이, 그리고 이 부품들로 구성된 복합부품인 LC 필터, RC 필터, 트랜스퍼머 등의 단일형, 또는 그 어레이에 있어서, 기판(10)위에 이 부품들의 기계적 고정이 다이본딩에 의해서 이루어지고, 단자간의 전기적 연결이 와이어 본딩에 의해 이루어지는 형태를 가진 수동부품, 복합 수동부품 및 그 어레이에 관한 것으로, 기존의 수동부품 또는 그 어레이는 표면실장법을 채택하여 탑재함으로서 단자간의 거리가 약 1.0mm 이하로 하기가 어려웠으나, 본 발명은 와이어 본딩에 의해 단자를 연결함으로서 단자간 거리를 200㎛ 이하까지 낮추는 것에 의해 단자의 선실장밀도를 5배이상 높일 수 있다. 또한, 반도체 칩과 동일한 방법으로 팩키징하므로 동일한 패키지 안에 한 모듈로서 패키지를 행할 수 있다.The present invention relates to an array-type passive chip component for wire bonding, that is, an array of resistors, capacitors, and inductors, and a single type or array thereof including an LC filter, an RC filter, a transformer, etc. 10) A passive component, a composite passive component, and an array thereof in which mechanical fixing of these components is made by die bonding, and an electrical connection between terminals is made by wire bonding. Although it was difficult to make the distance between terminals less than about 1.0mm by adopting the surface mounting method, the present invention reduces the line mounting density of terminals by lowering the distance between terminals to 200 μm or less by connecting the terminals by wire bonding. It can be increased five times or more. In addition, since the package is packaged in the same manner as the semiconductor chip, the package can be packaged as one module in the same package.

Description

와이어본딩용 어레이형 수동부품 제조방법Manufacturing method of array passive components for wire bonding

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도(a)~(d)는 본 발명에 따른 와이어본딩용 어레이형 수동 칩부품중 1005 크기의 칩에 5개의 저항이 어레이형태로 구성된 예로 박막 제조공정을 이용하여 나타낸 도면,2 (a) to (d) is a drawing showing an example in which five resistors are arranged in an array form on a chip of 1005 size among the array-type passive chip components for wire bonding according to the present invention using a thin film manufacturing process;

제3도(a)~(f)는 본 발명에 따른 와이어본딩용 어레이형 수동 칩부품중 1005 크기의 칩에 5개의 저항이 어레이형태로 구성된 예로 후막 제조공정을 이용하여 나타낸 도면이다.3 (a) to 3 (f) show an example in which five resistors are arranged in an array form on a 1005 size chip in an array type passive chip component for wire bonding according to the present invention using a thick film manufacturing process.

Claims (3)

기판(10)상에 광식각기술에 의해 감광저항체를 만들고, 증착법에 의한 Au코팅으로 단자부를 형성한 다음, 상기 감광저항체를 제거하는 단계와, 재차 감광저항체를 형성하여 스퍼터링 코팅한 다음, 상기 감광저항체를 제거하는 단계 및, 열처리에 의해 코팅층의 접착력을 증진시킨 다음, 그 위에 얇게 형성된 감광저항체의 저항치를 레이저 기공에 의해 맞춘후, 감광저항체를 제거한 다음, 보호층을 형성하는 단계로 이루어진 것을 특징으로 하는 와이어본딩용 어레이형 수동부품의 제조방법.After forming a photoresist on the substrate 10 by photolithography, forming a terminal portion by Au coating by vapor deposition, removing the photoresist, and again forming a photoresist and sputtering coating thereon, Removing the resistor and enhancing the adhesion of the coating layer by heat treatment, and then adjusting the resistance of the photoresist thinly formed thereon by laser pores, removing the photoresist, and then forming a protective layer. Method of manufacturing an array passive component for wire bonding. 기판(10)상에 하드마스크를 위치키시고, 증착법에 의한 Au, Ag/Pb 또는 Pt 코팅으로 증착과 더불어 단자전극의 형상을 형성하는 단계와, 재차, 저항소자 형상의 하드마스크를 위치시키고, 스퍼터링법에 의한 저항체 코팅으로 단자전극 사이에 저항체의 형상이 이루어지는 단계, 열처리에 의해 코팅층의 접착력을 증진시킨 다음, 그 위에 얇게 형성된 감광저항체의 저항치를 레이저 가공법에 의해 맞춘후, 감광저항체를 제거한 다음 보호층을 형성하는 단계로 이루어진 것을 특징으로 하는 와이어본딩용 어레이형 수동부품의 제조방법.Positioning the hard mask on the substrate 10, and forming the shape of the terminal electrode with the deposition by Au, Ag / Pb or Pt coating by the vapor deposition method, and again, to place a hard mask of the resistance element shape, After the resistor is formed by sputtering, the resistor is formed between the terminal electrodes. The adhesion of the coating layer is enhanced by heat treatment. A method of manufacturing an array type passive component for wire bonding, comprising the step of forming a protective layer. 기판(10)상에 후막전극용 페이스트 즉, Ag/Pb계 전극, 양 전극의 사이에 저항체 페이스트 및 저항 상에 보호층(보호 1층)용 유리질 페이스트를 후막인쇄하고 소성하는 단계와, 레이저식각법에 의해 소자 사이의 전극 물질을 제거하여 소자 사이의 전극을 분리하는 단계, 레이저식각법에 의해 소자의 저항을 측정하면서 원하는 저항치로 저항을 조절하는 단계, 레이저식각이 끝난 저항소자 상면에 보호층(보호 2층)용 유리질을 인쇄하고 마킹한 후 소성하는 단계, 기판(10)배면에 다이본딩용 Ni를 후막인쇄하고 소성하는 단계 및, 니켈 상에 Sn/Pb를 선택적으로 도포하여 플로우 또는 리플로우 공정에 의해 다이본딩이 이루어지는 단계로 이루어진 것을 특징으로 하는 와이어본딩용 어레이형 수동부품의 제조방법.Thick-film printing and firing a thick film electrode paste on the substrate 10, that is, an Ag / Pb-based electrode and a resistor paste between both electrodes, and a glassy paste for a protective layer (protective layer 1) on the resistor; Separating the electrode between the elements by removing the electrode material between the elements by a method, adjusting the resistance to a desired resistance value by measuring the resistance of the element by a laser etching method, a protective layer on the upper surface of the laser-etched resistance element Printing, marking and firing the glass for (protective two-layer), thick-printing and baking the die-bonding Ni on the back of the substrate 10, and selectively applying Sn / Pb on the nickel to flow or ripple Die-bonding is performed by a row process, the method of manufacturing an array-type passive component for wire bonding.
KR1019950028919A 1995-09-05 1995-09-05 Method for manufacturing chip resistor of array type for wirebonding KR0167009B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950028919A KR0167009B1 (en) 1995-09-05 1995-09-05 Method for manufacturing chip resistor of array type for wirebonding

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950028919A KR0167009B1 (en) 1995-09-05 1995-09-05 Method for manufacturing chip resistor of array type for wirebonding

Publications (2)

Publication Number Publication Date
KR970018288A true KR970018288A (en) 1997-04-30
KR0167009B1 KR0167009B1 (en) 1999-02-01

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100426702B1 (en) * 2001-08-27 2004-04-13 엘지이노텍 주식회사 Wire bonding structure using staircase multi-layer substrate

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100426702B1 (en) * 2001-08-27 2004-04-13 엘지이노텍 주식회사 Wire bonding structure using staircase multi-layer substrate

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KR0167009B1 (en) 1999-02-01

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