KR100426702B1 - Wire bonding structure using staircase multi-layer substrate - Google Patents
Wire bonding structure using staircase multi-layer substrate Download PDFInfo
- Publication number
- KR100426702B1 KR100426702B1 KR10-2001-0051717A KR20010051717A KR100426702B1 KR 100426702 B1 KR100426702 B1 KR 100426702B1 KR 20010051717 A KR20010051717 A KR 20010051717A KR 100426702 B1 KR100426702 B1 KR 100426702B1
- Authority
- KR
- South Korea
- Prior art keywords
- layer
- multilayer substrate
- wire bonding
- wire
- space portion
- Prior art date
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 42
- 239000004065 semiconductor Substances 0.000 claims abstract description 27
- 239000002184 metal Substances 0.000 claims abstract description 3
- 239000004020 conductor Substances 0.000 abstract 1
- 239000012778 molding material Substances 0.000 description 3
- 239000007769 metal material Substances 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/49105—Connecting at different heights
- H01L2224/49109—Connecting at different heights outside the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Abstract
본 발명은 계단식 다층 기판을 이용한 와이어 본딩 구조에 관한 것으로, 더욱 상세하게는 각 층에 패턴이 형성되고, 각 층이 적층된 상태에서 반도체 소자의 실장이 가능하도록 상면 중앙부에 공간부가 마련된 다층 기판과, 다층 기판의 공간부에 실장되고, 실장면의 층의 패턴과 와이어를 통해 전기적으로 접속되는 반도체 소자와, 다층 기판의 상면 층에 실장되는 복수의 표면 실장 디바이스와, 다층 기판의 상면에 결합되는 금속재의 케이스를 포함하는 전자 부품에 있어서, 상기 다층 기판은, 상기 공간부의 저면으로부터 양측 상면에 위치하는 각 층이 계단식으로 형성되며, 각 층의 상면에는 와이어 본딩 포인트가 실장되며, 상기 반도체 소자는, 상기 다층 기판의 공간부 저면에 실장되며, 상기 와이어는, 각 층에 형성된 와이어 본딩 포인트와 상기 반도체 소자의 상면에 본딩되는 것을 특징으로 한다.The present invention relates to a wire bonding structure using a stepped multilayer substrate, and more particularly, a pattern is formed in each layer, and a multilayer substrate having a space portion in a central portion of the upper surface so that semiconductor elements can be mounted in a stacked state of each layer; A semiconductor element mounted on a space portion of the multilayer substrate and electrically connected to the pattern of the layer of the mounting surface via a wire, a plurality of surface mounting devices mounted on the upper layer of the multilayer substrate, and coupled to the upper surface of the multilayer substrate. In an electronic component including a metal case, each layer positioned on both upper surfaces of the multi-layer substrate is formed in a stepped manner from a bottom of the space portion, and a wire bonding point is mounted on the upper surface of each layer. And a wire bonding point formed on each layer of the space portion of the multilayer substrate, and the wire It characterized in that bonded to the upper surface of the conductor elements.
따라서 상기와 같이 구성된 본 발명에 따르면 와이어의 길이로 인해 회로에 주는 영향을 최소화시켜 제품 성능을 개선시킬 수 있고, 와이어 길이를 최소화함으로써 비용 절감 효과가 발생되며, 다층의 와이어 본딩 포인트를 확보함으로써 회로 설계를 용이하게 할 수 있으며, 작업 능률을 향상시킬 수 있다.Therefore, according to the present invention configured as described above it is possible to improve the product performance by minimizing the effect on the circuit due to the length of the wire, cost reduction effect is generated by minimizing the wire length, the circuit by securing a multi-layer wire bonding point The design can be facilitated and work efficiency can be improved.
Description
본 발명은 와이어 본딩에 관한 것으로, 더욱 상세하게는 다층 기판에 반도체 소자를 실장할 때 다층 기판을 계단식으로 형성하고, 각 기판에 와이어 본딩 포인트를 형성함으로써 와이어의 길이를 단축시키도록 하는 계단식 다층 기판을 이용한 와이어 본딩 구조에 관한 것이다.The present invention relates to wire bonding, and more particularly, to form a multi-layered substrate in a stepped manner when mounting a semiconductor device on a multi-layered substrate, and to form a wire bonding point in each substrate to reduce the length of the wire stepped multi-layered substrate It relates to a wire bonding structure using.
일반적으로 다층 기판에 반도체 소자가 실장되는 전자 부품은 도 1에 도시된 바와 같이 각 층(A1~A5)에 패턴(P1~P6)이 형성되고, 각 층(A1~A5)이 적층된 상태에서 반도체 소자(20)의 실장이 가능하도록 상면 중앙부에 공간부(11)가 마련된 다층 기판(10)과, 다층 기판(10)의 공간부(11)에 실장되고, 실장면의 층(A4)의 패턴(P4)과 와이어(21)를 통해 전기적으로 접속되는 반도체 소자(bare chip)(20)와, 다층 기판(10)의 상면 층(A1)의 패턴(P1)에 실장되는 복수의 표면 실장 디바이스(30)와, 다층 기판(10)의 상면에 결합되는 금속재의 케이스(40)로 이루어진다. 여기에서 공간부(11)에는 반도체 소자(20)를 보호하기 위한 몰딩재(50)가 충진된다.In general, as shown in FIG. 1, an electronic component in which a semiconductor device is mounted on a multilayer substrate has a pattern P1 to P6 formed on each of the layers A1 to A5, and the layers A1 to A5 are stacked. In order to mount the semiconductor element 20, the multilayer substrate 10 having the space portion 11 provided in the center of the upper surface thereof is mounted, and the space portion 11 of the multilayer substrate 10 is mounted to form a layer A4 of the mounting surface. A plurality of surface mount devices mounted on a semiconductor chip 20 electrically connected through the pattern P4 and the wire 21 and the pattern P1 of the upper layer A1 of the multilayer substrate 10. 30 and a metal case 40 bonded to the upper surface of the multilayer substrate 10. Here, the space 11 is filled with a molding material 50 to protect the semiconductor device 20.
이러한 종래의 전자 부품은 반도체 소자가 다층 기판의 한 층에 실장되고, 실장된 층에 형성된 패턴과 반도체 소자가 와이어를 통해 연결된다. 그러기 때문에 와이어가 반도체 소자의 상면에서 실장면의 패턴에 본딩되기 때문에 반도체 소자만큼 높이 차에 의해 와이어의 길이가 늘어나게 되는데, 회로 특성상 와이어 길이가 단거리임을 요구하는 경우 와이어로 인해 회로 특성에 영향을 끼치는 문제점이 있다.In such a conventional electronic component, a semiconductor device is mounted on one layer of a multilayer substrate, and a pattern formed on the mounted layer and the semiconductor device are connected through a wire. Therefore, since the wire is bonded to the pattern of the mounting surface on the upper surface of the semiconductor device, the length of the wire is increased by the height difference as much as the semiconductor device.When the circuit characteristics require that the wire length is short, the wire affects the circuit characteristics. There is a problem.
또한 실장면에 복수의 와이어 본딩 포인트가 존재하기 때문에 회로 설계가 어렵고, 와이어의 공간 효율이 떨어져 작업 능률이 저하되는 다른 문제점이 있다.In addition, since there are a plurality of wire bonding points on the mounting surface, there is another problem that the circuit design is difficult, the space efficiency of the wire is low, and the work efficiency is reduced.
따라서 본 발명의 목적은 상기와 같은 문제점들을 해결하기 위한 것으로, 반도체 소자의 상면 또는 동일 위치에 존재하는 다층 기판을 계단식으로 형성하고, 각 층에 와이어 본딩 포인트를 형성하여 와이어의 길이를 단축시킴으로써 와이어로 인해 회로 특성이 영향을 받는 것을 차단하도록 하는데 있다.Accordingly, an object of the present invention is to solve the above problems, and by forming a multi-layered substrate on the upper surface or the same position of the semiconductor device in a stepwise manner, and forming a wire bonding point in each layer to shorten the wire length This prevents the circuit characteristics from being affected.
또한 각 층에 와이어 본딩 포인트를 형성함으로써 회로 설계가 용이하도록 하고, 작업 능률을 향상시키도록 하는데 있다.In addition, by forming a wire bonding point in each layer to facilitate the circuit design and improve the work efficiency.
도 1은 종래의 다층 기판을 이용한 와이어 본딩 구조를 설명하기 위한 반도체 소자의 정단면도1 is a cross-sectional front view of a semiconductor device for explaining a wire bonding structure using a conventional multilayer substrate.
도 2는 본 발명에 따른 계단식 다층 기판을 이용한 와이어 본딩 구조를 설명하기 위한 반도체 소자의 정단면도2 is a front sectional view of a semiconductor device for explaining a wire bonding structure using a stepped multilayer substrate according to the present invention.
<도면중 주요부분에 대한 부호의 설명><Description of the symbols for the main parts of the drawings>
110 : 다층 기판 111 : 공간부110: multilayer substrate 111: space part
120 : 반도체 소자 121 : 와이어120: semiconductor element 121: wire
130 : 표면 실장 디바이스 140 : 케이스130: surface mounting device 140: case
150 : 몰딩재 A10~A50 : 층150: molding material A10 ~ A50: layer
P10~P60 : 패턴P10 ~ P60: Pattern
상기와 같은 목적들을 달성하기 위한 본 발명의 특징은,Features of the present invention for achieving the above objects,
각 층마다 패턴이 형성되며, 중앙부에 공간부가 마련되도록 저면으로부터 양측 상면에 위치하는 각각 층이 계단식으로 형성되며, 각 층의 상면에 와이어 본딩 포인트가 형성되는 다층 기판과,A pattern is formed for each layer, and each layer positioned on both sides from the bottom is formed in a stepped manner so that a space portion is provided in the center, and a multi-layer substrate having wire bonding points formed on the upper surface of each layer;
상기 다층 기판의 공간부의 저면에 실장되고, 실장면의 층의 패턴과 각 층에 형성된 와이어 본딩 포인트와 상기 반도체 소자의 상면에 다수의 와이어가 본딩되어 전기적으로 접속되는 반도체 소자와,A semiconductor device mounted on a bottom surface of the space portion of the multilayer substrate, wherein a plurality of wires are bonded and electrically connected to a pattern of layers on the mounting surface, wire bonding points formed on each layer, and an upper surface of the semiconductor device;
상기 다층 기판의 최상위층에 실장되는 복수의 표면 실장 디바이스와,A plurality of surface mounting devices mounted on an uppermost layer of the multilayer substrate,
상기 다층 기판의 상면과 결합되는 금속재의 케이스로 구성되는 것을 특징으로 한다.Characterized in that the case is composed of a metal material coupled to the upper surface of the multilayer substrate.
이하, 본 발명에 의한 계단식 다층 기판을 이용한 와이어 본딩 구조를 도 2를 참조하여 상세하게 설명하기로 한다.Hereinafter, the wire bonding structure using the stepped multilayer substrate according to the present invention will be described in detail with reference to FIG. 2.
도 2는 본 발명에 따른 계단식 다층 기판을 이용한 와이어 본딩 구조를 설명하기 위한 반도체 소자의 정단면도이다.2 is a front sectional view of a semiconductor device for explaining a wire bonding structure using a stepped multilayer substrate according to the present invention.
도 2를 참조하면, 본 발명이 적용된 전자 부품(100)은, 다층 기판(110)과, 반도체 소자(bare chip)(120), 표면 실장 디바이스(130)와, 케이스(140)로 구성된다.다층 기판(110)은 각 층(A10~A50)마다 패턴(P10~P60)이 형성되며, 중앙부에 공간부(111)가 마련되도록 저면으로부터 양측 상면에 위치하는 각각 층이 계단식으로 형성되며, 계단식으로 형성된 각 층(A20, A30)의 패턴(P20, P30)에 와이어 본딩 포인트가 형성된다. 여기에서 공간부(111)에는 반도체 소자(120)를 보호하기 위한 몰딩재(150)가 충진된다.반도체 소자(120)는 다층 기판(110)의 공간부(111)의 저면에 실장되고, 계단식으로 형성된 각 층(A20, A30)의 와이어 본딩 포인트와 와이어(121)를 통해 전기적으로 접속된다.표면 실장 디바이스(130)는 다층 기판(110)의 상면 층(A10)의 패턴(P10)에 각각 실장된다.케이스는 다층 기판(110)의 상면과 결합된다.Referring to FIG. 2, the electronic component 100 to which the present invention is applied includes a multilayer substrate 110, a semiconductor chip 120, a surface mounting device 130, and a case 140. In the multilayer substrate 110, patterns P10 to P60 are formed for each layer A10 to A50, and each layer located on both sides from the bottom is formed in a stepped manner so that the space portion 111 is provided in the center. Wire bonding points are formed in the patterns P20 and P30 of each of the layers A20 and A30. Here, the space 111 is filled with a molding material 150 for protecting the semiconductor device 120. The semiconductor device 120 is mounted on the bottom surface of the space 111 of the multilayer substrate 110 and is stepped. The wire bonding points of the respective layers A20 and A30 formed through the wire 121 are electrically connected to each other. The surface mounting device 130 may be connected to the pattern P10 of the upper layer A10 of the multilayer substrate 110, respectively. The case is coupled to the top surface of the multilayer substrate 110.
이하 본 발명에 따른 계단식 다층 기판을 이용한 와이어 본딩 구조의 작용을 도 2를 참조하여 상세하게 설명하면 다음과 같다.Hereinafter, the operation of the wire bonding structure using the stepped multilayer substrate according to the present invention will be described in detail with reference to FIG. 2.
도 2에 도시된 바와 같이 다층 기판(110)의 공간부(111)가 계단식으로 형성되고, 계단식으로 형성된 각 층(A20, A30)의 패턴(P20, P30)에 와이어 본딩 포인트가 분산되어 형성되기 때문에, 반도체 소자(120)를 공간부(111)의 저면에 실장후 와이어(121)를 본딩하게 되면, 와이어(121)가 반도체 소자(120)의 상면에서 반도체 소자(120)와 동일 높이 또는 이보다 높은 곳에 위치한 각 층(A20, A30)의 와이어 본딩 포인트에 본딩되기 때문에 와이어(121)의 길이가 상대적으로 짧아진다.As shown in FIG. 2, the space 111 of the multilayer substrate 110 is formed in a stepped manner, and wire bonding points are dispersed in patterns P20 and P30 of each of the stepped layers A20 and A30. Therefore, when the semiconductor device 120 is bonded to the bottom surface of the space 111 and then the wire 121 is bonded, the wire 121 is the same height or higher than the semiconductor device 120 on the upper surface of the semiconductor device 120. The length of the wire 121 is relatively short because it is bonded to the wire bonding point of each layer (A20, A30) located at a high position.
그러기 때문에 와이어의 길이로 인해 회로에 주는 영향을 최소화시켜 제품 성능을 개선시킬 수 있고, 와이어 길이를 최소화함으로써 비용 절감 효과가 발생�U>�/U>며, 다층의 와이어 본딩 포인트를 확보함으로써 회로 설계를 용이하게 할 수 있으며, 와이어 본딩 포인트가 넓게 형성되어 있어 작업 능률을 향상시킬 수 있다.This minimizes the impact on the circuit due to the length of the wire, improving product performance, reducing cost by minimizing the wire length, and securing multiple circuit bonding points. The design can be facilitated, and the wire bonding points are widely formed to improve the work efficiency.
이상에서 설명한 바와 같이 본 발명에 따른 계단식 다층 기판을 이용한 와이어 본딩 구조에 의하면, 반도체 소자의 상면 또는 동일 위치에 존재하는 다층 기판을 계단식으로 형성하고, 각 층에 와이어 본딩 포인트를 형성하여 와이어의 길이를 단축시킴으로써 와이어로 인해 회로 특성이 영향을 받는 것을 차단할 수 있다.As described above, according to the wire bonding structure using the stepped multilayer substrate according to the present invention, the multi-layered substrate existing on the upper surface or the same position of the semiconductor device is formed stepwise, and the wire bonding point is formed on each layer to length the wire. By shortening it, the wires can be prevented from affecting circuit characteristics.
또한 각 층에 와이어 본딩 포인트를 형성함으로써 회로 설계가 용이하도록 하고, 작업 능률을 향상시킬 수 있다.In addition, by forming wire bonding points in each layer, it is easy to design the circuit and improve the work efficiency.
Claims (1)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR10-2001-0051717A KR100426702B1 (en) | 2001-08-27 | 2001-08-27 | Wire bonding structure using staircase multi-layer substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR10-2001-0051717A KR100426702B1 (en) | 2001-08-27 | 2001-08-27 | Wire bonding structure using staircase multi-layer substrate |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR20030018145A KR20030018145A (en) | 2003-03-06 |
| KR100426702B1 true KR100426702B1 (en) | 2004-04-13 |
Family
ID=27720961
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR10-2001-0051717A KR100426702B1 (en) | 2001-08-27 | 2001-08-27 | Wire bonding structure using staircase multi-layer substrate |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR100426702B1 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103558903A (en) * | 2013-11-12 | 2014-02-05 | 上海航天测控通信研究所 | PowerPC (Personal Computer) module with radiation resisting performance |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR970018288A (en) * | 1995-09-05 | 1997-04-30 | 우덕창 | Manufacturing method of array passive components for wire bonding |
-
2001
- 2001-08-27 KR KR10-2001-0051717A patent/KR100426702B1/en not_active IP Right Cessation
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR970018288A (en) * | 1995-09-05 | 1997-04-30 | 우덕창 | Manufacturing method of array passive components for wire bonding |
Also Published As
| Publication number | Publication date |
|---|---|
| KR20030018145A (en) | 2003-03-06 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6489669B2 (en) | Integrated circuit device | |
| US6756664B2 (en) | Noise eliminating system on chip and method of making same | |
| US7411278B2 (en) | Package device with electromagnetic interference shield | |
| KR20090123680A (en) | Stacked semiconductor package | |
| US20120228011A1 (en) | Semiconductor Load Board | |
| TWI704858B (en) | Electronic module | |
| KR20010049663A (en) | Semiconductor device | |
| US10880987B2 (en) | Circuit board and optical module having such circuit board | |
| KR100426702B1 (en) | Wire bonding structure using staircase multi-layer substrate | |
| US6127728A (en) | Single reference plane plastic ball grid array package | |
| US20080128881A1 (en) | Semiconductor device | |
| KR100833184B1 (en) | Stacked semiconductor package | |
| KR100725517B1 (en) | multi-layered circuit substrate having bonding pads and ball lands arranged on two or more layers, and semiconductor package structure using the same | |
| JP4813786B2 (en) | Integrated circuit and integrated circuit assembly | |
| JP4359110B2 (en) | Circuit equipment | |
| US20200329565A1 (en) | Package carrier and package structure | |
| JP3290754B2 (en) | Multilayer substrate for semiconductor mounting | |
| KR100639947B1 (en) | Printed circuit board and manufacturing method thereof | |
| KR100762908B1 (en) | Substrate for bga type package | |
| TW202038387A (en) | Package carrier and package structure | |
| KR100388291B1 (en) | Structure of semiconductor package | |
| KR100525452B1 (en) | Semiconductor package & PCB mounted with the same | |
| KR20020074792A (en) | Stacked semiconductor package | |
| KR20070076775A (en) | Multi-layer printed circuit board anc semiconductor package having the same | |
| KR20090013386A (en) | Multi chip packages |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| E902 | Notification of reason for refusal | ||
| E701 | Decision to grant or registration of patent right | ||
| GRNT | Written decision to grant | ||
| FPAY | Annual fee payment |
Payment date: 20121210 Year of fee payment: 10 |
|
| FPAY | Annual fee payment |
Payment date: 20140206 Year of fee payment: 11 |
|
| FPAY | Annual fee payment |
Payment date: 20150205 Year of fee payment: 12 |
|
| FPAY | Annual fee payment |
Payment date: 20160205 Year of fee payment: 13 |
|
| FPAY | Annual fee payment |
Payment date: 20170207 Year of fee payment: 14 |
|
| LAPS | Lapse due to unpaid annual fee |