KR970013753A - Interrupt Generation Circuit - Google Patents

Interrupt Generation Circuit Download PDF

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Publication number
KR970013753A
KR970013753A KR1019950025254A KR19950025254A KR970013753A KR 970013753 A KR970013753 A KR 970013753A KR 1019950025254 A KR1019950025254 A KR 1019950025254A KR 19950025254 A KR19950025254 A KR 19950025254A KR 970013753 A KR970013753 A KR 970013753A
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South Korea
Prior art keywords
interrupt
external input
input pin
signal
determination circuit
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KR1019950025254A
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Korean (ko)
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KR0157894B1 (en
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홍상표
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문정환
엘지반도체 주식회사
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Priority to KR1019950025254A priority Critical patent/KR0157894B1/en
Publication of KR970013753A publication Critical patent/KR970013753A/en
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Publication of KR0157894B1 publication Critical patent/KR0157894B1/en

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/24—Handling requests for interconnection or transfer for access to input/output bus using interrupt
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/3243—Power saving in microcontroller unit

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Electronic Switches (AREA)
  • Logic Circuits (AREA)

Abstract

본 발명은 인터럽트 발생회로에 관한 것으로, 종래의 회로는 외부입력핀 중 한개 또는 한개 이상이 액티브 상태가 되면 인터럽트요구 신호가 발생되기 때문에 전력을 많이 소비하게 되는 문제점이 있었다. 본 발명은 이러한 종래의 문제점을 해결하기 위해 풀업저항이 각기 접속된 외부입력핀과; 상기 외부입력핀 중에서 어느 하나라도 액티브되면 이를 감지하여 그에 따른 감지신호를 출력하는 제1인터럽트 판별회로부와; 상기 제1인터럽트 판별회로부의 출력신호에 따라 상기 외부입력핀의 신호중 외부입력핀 또는 외부입력핀의 출력신호를 선택하여 전달하는 인터럽트 스위치부와; 상기 인터럽트 스위치부의 출력신호 중에서 액티브신호가 오직 한개인지 또는 두개이상인지를 감지하여 그에 따른 신호를 출력하는 제2인터럽트 판별회로부와; 상기 제1 및 제2인터럽트 판별회로부의 출력신호를 앤드조합하여 인터럽트 요구신호를 발생하는 앤드게이트로 구성하여 외부입력핀이 오직 하나만 액티브상태일 때 인터럽트요구 신호를 발생하도록 함으로써 소비전력을 줄일 수 있는 인터럽트 발생회로를 창안한 것이다.The present invention relates to an interrupt generating circuit, and a conventional circuit has a problem in that a large amount of power is consumed because an interrupt request signal is generated when one or more of an external input pin becomes active. The present invention and the external input pin is connected to each pull-up resistor to solve the conventional problems; A first interrupt determination circuit unit for detecting any one of the external input pins and outputting a detection signal accordingly; An interrupt switch unit which selects and transmits an external input pin or an output signal of an external input pin among the signals of the external input pin according to the output signal of the first interrupt determination circuit unit; A second interrupt determination circuit unit for detecting whether there is only one active signal or two or more active signals among the output signals of the interrupt switch unit, and outputting a corresponding signal; By combining the output signals of the first and second interrupt discrimination circuit units with an AND gate that generates an interrupt request signal, the interrupt request signal is generated when only one external input pin is active, thereby reducing power consumption. The interrupt generation circuit was created.

Description

인터럽트 발생회로Interrupt Generation Circuit

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 본 발명의 인터럽트 발생회로도.2 is an interrupt generation circuit diagram of the present invention.

제3도는 본 발명에 있어서, 인터럽트 스위치부의 상세 회로도.3 is a detailed circuit diagram of an interrupt switch unit in the present invention.

Claims (5)

풀업저항(R0-R7)이 각기 접속된 외부입력핀(I0-I7)과; 상기 외부입력핀(I0-I7) 중에서 어느 하나라도 액티브되면 이를 감지하여 그에 따른 감지신호를 출력하는 제1인터럽트 판별회로부(100)와; 상기 제1인터럽트 판별회로부(100)의 출력신호에 따라 상기 외부입력핀(I0-I7)의 신호중 외부입력핀(I0-I3) 또는 외부 입력핀(I4-I7)의 출력신호를 선택하여 전달하는 인터럽트 스위치부(200)와; 상기 인터럽트 스위치부(200)의 출력신호 중에서 액티브신호가 오직 한개인지 또는 두개이상인지를 감지하여 그에따른 신호를 출력하는 제2인터럽트 판별회로부(300)와; 상기 제1 및 제2인터럽트 판별회로부(100, 300)의 출력신호를 앤드조합하여 인터럽트 요구 신호를 발생하는 앤드게이트(AND5)로 구성한 것을 특징으로 하는 인터럽트 발생회로.External input pins I0-I7 to which pull-up resistors R0-R7 are connected; A first interrupt determination circuit unit (100) which detects any one of the external input pins (I0-I7) when it is activated and outputs a detection signal accordingly; According to the output signal of the first interrupt determination circuit unit 100 to select and transmit the output signal of the external input pin (I0-I3) or the external input pin (I4-I7) of the signal of the external input pin (I0-I7). An interrupt switch unit 200; A second interrupt determination circuit unit 300 for detecting whether there is only one active signal or two or more active signals among the output signals of the interrupt switch unit 200, and outputting a corresponding signal; And an AND gate (AND5) for generating an interrupt request signal by AND combining the output signals of the first and second interrupt determination circuit sections (100, 300). 제1항에 있어서, 제1인터럽트 판별회로부(100)는 외부입력핀(I0-I3)의 출력신호를 입력받아 이를 낸드조합하여 출력하는 낸드게이트(ND1)와; 외부입력핀(I4-I7)의 출력신호를 입력받아 이를 낸드조합하여 출력하는 낸드게이트(ND2)와; 상기 낸드게이트(ND1, ND2)의 출력신호를 입력받아 이를 배타적논리합하여 출려하는 배타적오아게이트(XOR1)로 구성한 것을 특징으로 하는 인터럽트 발생회로.The first interrupt determination circuit unit 100 includes: a NAND gate ND1 for receiving an output signal of an external input pin I0-I3 and NAND-combining the output signal; A NAND gate ND2 for receiving an output signal of the external input pins I4-I7 and NAND-combining the output signal; And an exclusive ogate (XOR1) configured to receive an output signal of the NAND gates (ND1, ND2) and output an exclusive logic sum. 제1항에 있어서, 인터럽트 스위치부(200)는 상기 제1인터럽트 판별회로부(100)의 낸드게이트(ND1)이 출력신호에 따라 외부입력핀(I0-I3) 또는 외부입력핀(I4-I7)의 출력신호를 선택하여 전송하는 전송게이트(TG1-TG8)로 구성한 것을 특징으로 하는 인터럽트 발생회로.According to claim 1, the interrupt switch unit 200 is the NAND gate ND1 of the first interrupt determination circuit unit 100 according to the output signal of the external input pin (I0-I3) or external input pin (I4-I7). And a transmission gate (TG1-TG8) for selecting and transmitting an output signal of the interrupt generator. 제1항에 있어서, 제2인터럽트 판별회로부(300)는 4개단위로 상기 인터럽트 스위치부(200)의 출력신호를 입력받아 이를 타측단자의 입력신호와 배타적노아링하여 출력하는 배타적노아게이트(XNOR1-XNOR16)와; 상기 배타적노아게이트(XNOR1-XNOR16)의 출력신호를 4개단위로 입력받아 이를 논리곱하여 출력하는 앤드게이트(AND1-AND4)와; 상기 앤드게이트(AND1-AND4)의 출력신호를 논리합하여 출력하는 오아게이트(OR1)로 구성한 것을 특징으로 하는 인터럽트 발생회로.The exclusive interrupt gate of claim 1, wherein the second interrupt determination circuit unit 300 receives the output signals of the interrupt switch unit 200 in four units and outputs them by exclusively ringing the input signals of the other terminals. -XNOR16); An AND gate (AND1-AND4) receiving the output signals of the exclusive NOR gates (XNOR1-XNOR16) in four units and performing a logical multiplication on the output signals; And an OR gate (OR1) for ORing and outputting the output signals of the AND gates (AND1-AND4). 제4항에 있어서, 배타적노아게치트(XNOR1, XNOR6, XNOR11, XNOR16)의타측단자에는 소스전압(VSS)이 인가되고, 배타적노아게이트(XNOR2-XNOR4, XNOR5, XNOR7, XNOR8, XNOR9, XNOR10, XNOR12, XNOR13-XNOR15)의 타측단자에는 전원전압(VCC)이 인가되는 것을 특징으로 하는 인터럽트 발생회로.5. The source terminal (VSS) is applied to the other terminals of the exclusive no-gauge (XNOR1, XNOR6, XNOR11, XNOR16), and the exclusive no-gates (XNOR2-XNOR4, XNOR5, XNOR7, XNOR8, XNOR9, XNOR10, An interrupt generating circuit, characterized in that a power supply voltage VCC is applied to the other terminal of XNOR12 and XNOR13-XNOR15. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950025254A 1995-08-17 1995-08-17 Interrupt generating circuit KR0157894B1 (en)

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Application Number Priority Date Filing Date Title
KR1019950025254A KR0157894B1 (en) 1995-08-17 1995-08-17 Interrupt generating circuit

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Application Number Priority Date Filing Date Title
KR1019950025254A KR0157894B1 (en) 1995-08-17 1995-08-17 Interrupt generating circuit

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KR970013753A true KR970013753A (en) 1997-03-29
KR0157894B1 KR0157894B1 (en) 1998-12-15

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