KR970013730A - Address buffering method and apparatus - Google Patents

Address buffering method and apparatus Download PDF

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Publication number
KR970013730A
KR970013730A KR1019950025434A KR19950025434A KR970013730A KR 970013730 A KR970013730 A KR 970013730A KR 1019950025434 A KR1019950025434 A KR 1019950025434A KR 19950025434 A KR19950025434 A KR 19950025434A KR 970013730 A KR970013730 A KR 970013730A
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KR
South Korea
Prior art keywords
address signal
level
input
buffering
address
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KR1019950025434A
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Korean (ko)
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KR0160923B1 (en
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김태윤
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김주용
현대전자산업 주식회사
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Priority to KR1019950025434A priority Critical patent/KR0160923B1/en
Publication of KR970013730A publication Critical patent/KR970013730A/en
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Publication of KR0160923B1 publication Critical patent/KR0160923B1/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/06—Address interface arrangements, e.g. address buffers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0008—Arrangements for reducing power consumption
    • H03K19/0013—Arrangements for reducing power consumption in field effect transistor circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018507—Interface arrangements
    • H03K19/018521—Interface arrangements of complementary type, e.g. CMOS

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Dram (AREA)

Abstract

본 발명은 반도체 메모리 장치의 어드레스 버퍼링 방법 및 그 장치에 관한 것으로, 외부 어드레스인 an을 버퍼링 할때는 TTL레벨의 중간 레벨인 기준 전위를 이용하여 기준 전위보다 높은 an레벨이 입력되면 하이로 인식하고 기준 전위보다 낮은 an레벨이 입력되면 로우로 인식하여 어드레스 버퍼링을 함으로써, 외부 어드레스 신호가 TTL레벨이어서 하이 레벨과 로우 레벨의 차이가 적더라도 버퍼링이 이루어지고 또 노이즈 성분이 있더라도 지장이 없는 반면에, CMOS레벨로서 하이 레벨과 로우 레벨의 차이가 Vcc와 Vss로 확실하게 차이가 나는 내부 어드레스 입력 신호를 버퍼링하는 모드에서는 기준 전위는 사용하지 않고 어드레스 발생기에서 만들어지는 bnb라는 신호를 이용하여 버퍼링하도록 구현함으로써, 전력소모를 줄일 수 있을 뿐만 아니라 동작속도를 향상시키는 효과가 있다.The present invention relates to an address buffering method of a semiconductor memory device and a device thereof. When buffering an external address an, if an level higher than the reference potential is input by using a reference potential which is an intermediate level of the TTL level, the present invention is recognized as a high and the reference potential. When the lower an level is input, it is recognized as low and address buffered, so that even if the external address signal is a TTL level, even if the difference between the high level and the low level is small, buffering is performed and there is no problem even if there is a noise component. In the mode of buffering the internal address input signal where the difference between the high level and the low level is clearly different between Vcc and Vss, the power is implemented by using the signal bnb generated by the address generator without using the reference potential. Not only can reduce the consumption, but also the operating speed Has the effect of improving.

Description

어드레스 버퍼링 방법 및 그 장치Address buffering method and apparatus

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 본 발명의 일실시예에 따른 어드레스 버퍼의 회로도.2 is a circuit diagram of an address buffer according to an embodiment of the present invention.

Claims (5)

반도체 메모리 장치로 입력되는 외부 어드레스 신호와 내부 어드레스 신호를 각기 따로 버퍼링하기 위한 어드레스 버퍼링 방법에 있어서, 상기 외부 어드레스 신호가 입력이 되면 기준전위를 이용하여 이 기준전위보다 높은 외부 어드레스 신호가 입력되면 제1 상태로 인식하고 기준전위보다 낮은 외부 어드레스 신호가 입력되면 제2 상태로 인식하여 어드레스 버퍼링하는 제1과정과, 상기 내부 어드레스 신호가 입력이 되면 기준전위를 사용하지 않고 내부 어드레스 발생기에서 만들어지는 내부 어드레스 신호를 이용하여 버퍼링하는 제2 과정을 포함하는 것을 특징으로 하는 어드레스 버퍼링 방법.An address buffering method for separately buffering an external address signal and an internal address signal input to a semiconductor memory device, wherein the external address signal is inputted when an external address signal higher than the reference potential is input using a reference potential. A first process of recognizing as a state 1 and buffering an address when the external address signal is lower than the reference potential is input; and an internally generated by an internal address generator without using a reference potential when the internal address signal is input. And a second process of buffering using the address signal. 제1항에 있어서, 상기 외부 어드레스 신호는 TTL레벨(0.8∼20.V)이고, 상기 내부 어드레스 신호는 CMOS레벨(Vcc~Vss)인 것을 특징으로 하는 어드레스 버퍼링 방법.The address buffering method according to claim 1, wherein the external address signal has a TTL level (0.8 to 20 V) and the internal address signal has a CMOS level (Vcc to Vss). 제1항에 있어서, 상기 제1 상태는 하이, 제2 상태는 로우인 것을 특징으로 하는 어드레스 버퍼링 방법.The method of claim 1, wherein the first state is high and the second state is low. 제1항에 있어서, 상기 내부 어드레스 발생기에서 만들어지는 내부 어드레스 신호는 상기 최초 입력되는 내부 어드레스 신호와 그 전위 레벨이 반대인 것을 특징으로 하는 어드레스 버퍼링 방법.The address buffering method of claim 1, wherein the internal address signal generated by the internal address generator is opposite in potential level to the first input internal address signal. 반도체 메모리 장치의 어드레스 버퍼회로가 전력소모를 줄이거나 동작속도를 향상시키기 위하여, TTL레벨인 외부 어드레스 신호가 입력이 될때는 기준전위와 비교하여 버퍼링하도록 하고, CMOS레벨인 내부 어드레스 신호가 입력이 될때는 내부 어드레스 발생기에서 만들어지는 내부 어드레스 신호와 비교하여 버퍼링하는 것을 특징으로 하는 어드레스 버퍼장치.When the address buffer circuit of the semiconductor memory device reduces power consumption or improves the operation speed, when the external address signal having the TTL level is input, the buffer is compared with the reference potential and when the internal address signal having the CMOS level is input. Is buffered in comparison with an internal address signal produced by an internal address generator. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950025434A 1995-08-18 1995-08-18 Address buffering method and apparatus KR0160923B1 (en)

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KR1019950025434A KR0160923B1 (en) 1995-08-18 1995-08-18 Address buffering method and apparatus

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Application Number Priority Date Filing Date Title
KR1019950025434A KR0160923B1 (en) 1995-08-18 1995-08-18 Address buffering method and apparatus

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KR970013730A true KR970013730A (en) 1997-03-29
KR0160923B1 KR0160923B1 (en) 1999-03-20

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