KR970013317A - Method of manufacturing semiconductor device having initial P well structure - Google Patents

Method of manufacturing semiconductor device having initial P well structure Download PDF

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Publication number
KR970013317A
KR970013317A KR1019950023847A KR19950023847A KR970013317A KR 970013317 A KR970013317 A KR 970013317A KR 1019950023847 A KR1019950023847 A KR 1019950023847A KR 19950023847 A KR19950023847 A KR 19950023847A KR 970013317 A KR970013317 A KR 970013317A
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KR
South Korea
Prior art keywords
forming
conductive
ion layer
impurity ion
well
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Application number
KR1019950023847A
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Korean (ko)
Inventor
박종성
이경호
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문정환
엘지반도체 주식회사
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Priority to KR1019950023847A priority Critical patent/KR970013317A/en
Publication of KR970013317A publication Critical patent/KR970013317A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823493—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
    • H10B12/0335—Making a connection between the transistor and the capacitor, e.g. plug

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Semiconductor Memories (AREA)

Abstract

본 발명은 반도체 소자 제조방법에 관한 것으로, 특히 P형웰을 초기에 형성하는 공정으로 반도체 소자를 제조하여 전극 형성등의 후 공정시에 단차를 개선하도록 한 초기 P형웰구조를 갖는 반도체 소자 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device having an initial P-type well structure in which a semiconductor device is manufactured in an initial step of forming a P-type well to improve the step difference in a subsequent process such as forming an electrode. It is about.

상기 목적을 달성하기 위한 본 발명의 초기 P형웰 구조를 갖는 반도체 소자 제조방법은 제1절연막과 질화막이 증착된 실리콘기판의 소정 부위에 제1불순물 이온층을 형성하는 제1공정과, 상기 제1불순물 이온층 상부에 1000Å∼5000Å의 두께로 제2절연막을 형성하는 제2공정과, 상기 제2절연막, 상기 제1불순물 이온층과 이웃한 실리콘기판에 제2불순물 이온층이 형성되는 제3공정과, 상기 제1불순물 이온층과 상기 제2불순물 이온층에 열확산 공정을 실시하여 반도체 기판 깊숙한 일정영역에 제1도전형웰과 제2도전형웰을 형성하는 제4공정과, 상기 제1도전형웰과 제2도전형웰 상부에 각각 문턱전압조절용 제2도전형 제1불순물 이온층과 제1도전형 제1불순물 이온층을 형성하는 제5공정과, 상기 제1도전형웰과 제2도전형웰의 소정 부위에 게이트전극 양측에 제1도전형 제2불순물 이온층을 형성하는 제6공정과, 상기 제2도전형 제2불순물 이온층의 일측에 콘택되도록 제2절연막에 콘택홀을 형성하여 비트라인을 형성하는 제7공정과, 상기 제2도전형 제2불순물 이온층이 다른 일측에 콘택되도록 제3절연막에 콘택홀을 형성하여 스토리지전극을 형성하는 제8공정과, 상기 스토리지전극 표면에 유전체막을 형성하여 그위에 플레이트전극을 형성하는 제9공정을 포함하여 이루어짐을 특징으로 한다.A semiconductor device manufacturing method having an initial P-type well structure of the present invention for achieving the above object comprises a first step of forming a first impurity ion layer on a predetermined portion of a silicon substrate on which a first insulating film and a nitride film are deposited; A second step of forming a second insulating film having a thickness of 1000 m to 5000 m over the ion layer, a third step of forming a second impurity ion layer on a silicon substrate adjacent to the second insulating film and the first impurity ion layer, and the second step Performing a thermal diffusion process on the first impurity ion layer and the second impurity ion layer to form a first conductive well and a second conductive well in a predetermined region deep within the semiconductor substrate, and on the first conductive well and the second conductive well Forming a second conductive first impurity ion layer and a first conductive first impurity ion layer for threshold voltage adjustment, respectively; and a predetermined portion of the first conductive well and the second conductive well on both sides of the gate electrode A sixth step of forming a first conductive second impurity ion layer, a seventh step of forming a bit line by forming a contact hole in a second insulating film so as to contact one side of the second conductive second impurity ion layer, and the second step An eighth step of forming a storage electrode by forming a contact hole in the third insulating layer so that the second conductive impurity ion layer contacts the other side; and a ninth step of forming a dielectric layer on the surface of the storage electrode to form a plate electrode thereon. Characterized in that the process comprises a.

Description

초기 피(P)형웰 구조를 갖는 반도체 소자 제조방법Method of manufacturing semiconductor device having initial P well structure

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 본 발명의 초기 P형웰 구조를 갖는 반도체 소자 제조방법.2 is a semiconductor device manufacturing method having an initial P-type well structure of the present invention.

Claims (1)

제1절연막과 질화막이 증착된 실리콘기판의 소정 부위에 제1불순물 이온층을 형성하는 제1공정과, 상기 제1불순물 이온층 상부에 1000Å∼5000Å의 두께로 제2절연막을 형성하는 제2공정과, 상기 제2절연막, 상기 제1불순물 이온층과 이웃한 실리콘기판에 제2불순물 이온층이 형성되는 제3공정과, 상기 제1불순물 이온층과 상기 제2불순물 이온층에 열확산 공정을 실시하여 반도체기판 깊숙한 일정영역에 제1도전형웰과 제2도전형웰을 형성하는 제4공정과, 상기 제1도전형웰과 제2도전형웰 상부에 각각 문턱전압조절용 제2도전형 제1불순물 이온층과 제1도전형 제1불순물 이온층을 형성하는 제5공정과, 상기 제1도전형웰과 제2도전형웰 소정 부위에 게이트 전극을 형성하고, 상기 제1도전형웰의 게이트전극 양측에 제2도전형 제2불순물 이온층과, 상기 제2도전형의 게이트전극 양측에 제1도전형 제2불순물 이온층을 형성하는 제6공정고, 상기 제2도전형 제2불순물 이온층의 일측에 콘택되도록 제2절연막에 콘택홀을 형성하여 비트라인을 형성하는 제7공정과, 상기 제2도전형 제2불순물 이온층의 다른 일측에 콘택되도록 제3절연막에 콘택홀을 형성하여 스토리지전극을 형성하는 제8정과, 상기 스토리지전극 표면에 유전체막을 형성하여 그위에 플레이트전극을 형성하는 제9공정을 포함하여 이루어짐을 특징으로 하는 초기 P형웰 구조를 갖는 반도체 소자 제조방법.A first step of forming a first impurity ion layer on a predetermined portion of the silicon substrate on which the first insulating film and the nitride film are deposited, and a second step of forming a second insulating film on the first impurity ion layer with a thickness of 1000 kV to 5000 kPa; A third region in which a second impurity ion layer is formed on a silicon substrate adjacent to the second insulating layer and the first impurity ion layer, and a thermal diffusion process is performed on the first impurity ion layer and the second impurity ion layer to a predetermined region deep in a semiconductor substrate A fourth process of forming a first conductive well and a second conductive well in the first conductive well, and a second conductive first impurity ion layer and a first conductive first impurity for adjusting a threshold voltage on the first conductive well and the second conductive well, respectively. A fifth step of forming an ion layer, a gate electrode formed on predetermined portions of the first conductive well and the second conductive well, and a second conductive second impurity ion layer on both sides of the gate electrode of the first conductive well; 2nd Challenge A sixth step of forming a first conductive second impurity ion layer on both sides of the gate electrode of the second electrode; and forming a bit line by forming a contact hole in the second insulating layer so as to contact one side of the second conductive second impurity ion layer. A seventh step of forming a storage electrode by forming a contact hole in a third insulating film so as to contact the other side of the second conductive type impurity ion layer, and forming a dielectric film on the surface of the storage electrode, and forming a plate electrode thereon. Method for manufacturing a semiconductor device having an initial P-type well structure, characterized in that comprises a ninth step of forming.
KR1019950023847A 1995-08-02 1995-08-02 Method of manufacturing semiconductor device having initial P well structure KR970013317A (en)

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