KR970013198A - 반도체 소자의 소자분리절연막 형성방법 - Google Patents

반도체 소자의 소자분리절연막 형성방법 Download PDF

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KR970013198A
KR970013198A KR1019950026729A KR19950026729A KR970013198A KR 970013198 A KR970013198 A KR 970013198A KR 1019950026729 A KR1019950026729 A KR 1019950026729A KR 19950026729 A KR19950026729 A KR 19950026729A KR 970013198 A KR970013198 A KR 970013198A
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insulating film
forming
trench
semiconductor substrate
insulating layer
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KR1019950026729A
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KR100197648B1 (ko
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장세억
송태식
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김주용
현대전자산업주식회사
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Priority to KR1019950026729A priority Critical patent/KR100197648B1/ko
Priority to US08/702,062 priority patent/US5637529A/en
Priority to JP8240974A priority patent/JP2682529B2/ja
Publication of KR970013198A publication Critical patent/KR970013198A/ko
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Publication of KR100197648B1 publication Critical patent/KR100197648B1/ko

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
    • H01L21/02233—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/02255—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by thermal treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02299—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314—Inorganic layers
    • H01L21/316—Inorganic layers composed of oxides or glassy oxides or oxide based glass
    • H01L21/3165—Inorganic layers composed of oxides or glassy oxides or oxide based glass formed by oxidation
    • H01L21/31654—Inorganic layers composed of oxides or glassy oxides or oxide based glass formed by oxidation of semiconductor materials, e.g. the body itself
    • H01L21/31658—Inorganic layers composed of oxides or glassy oxides or oxide based glass formed by oxidation of semiconductor materials, e.g. the body itself by thermal oxidation, e.g. of SiGe
    • H01L21/31662—Inorganic layers composed of oxides or glassy oxides or oxide based glass formed by oxidation of semiconductor materials, e.g. the body itself by thermal oxidation, e.g. of SiGe of silicon in uncombined form
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H01L21/76213—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Element Separation (AREA)
  • Local Oxidation Of Silicon (AREA)

Abstract

본 발명은 반도체 소자의 소자분리절연막 형성방법에 관한 것으로, 반도체기판 상부에 패드산화막, 및 제1절연막을 순차적으로 형성하고 상기 반도체기판의 비활성영역을 노출시키는 식각공정으로 제1절연막패턴을 형성한 다음, 상기 제1절연막패턴 측벽에 제2절연막 스페이서를 형성하고 상기 제2절연막패턴과 제2절연막 스페이서를 마스크로하여 상기 반도체기판을 삭각하여 트렌치를 형성한 다음, 수산화암모늄을 이용한 습식방법이나 불순물주입공정 및 SPE 공정으로 상기 트렌치 형성공정시 발생되는 격자결함을 제거하고 열산화공정으로 소자 분리절연막을 형성하여 접합누설전류를 감소시킴으로써 반도체 소자의 수율, 신뢰성 및 생산성을 향상시키고 반도체 소자의 고집적화를 가능하게 하는 기술이다.

Description

반도체 소자의 소자분리절연막 형성방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1a도 내지 제1c도는 본 발명의 제1실시예에 따른 반도체 소자의소자분리절연막 형성공정을 도시한 단면도,
제2a도 내지 제2c도는 본 발명의 제2실시예에 따른 반도체 소자의 소자분리절연막 형성공정을 도시한 단면도

Claims (8)

  1. 반도체기판 상부에 패드산화막 및 제1절연막을 형성하는 공정과, 상기 반도체기판의 비활성영역이 노출되는 제1절연막패턴을 형성하는 공정과, 상기 제1절연막 측벽에 제2절연막 스페이서를 형성하는 공정과, 상기 제1절연막패턴과 제2절연막 스페이서를 마스크로하여 상기 반도체기판을 일정두께 식각하여 트렌치를 형성하는 공정과, 상기 트렌치 형성공정시 발생되는 격자결함을 제거하기 위하여 수산화암모늄용액을 이용한 습식방법으로 상기 격자결함을 제거하는 공정과, 열산화공정으로 상기 트렌치에 소자분리절연막을 형성하는 공정을 포함하는 반도체 소자의 소자분리절연막 형성방법
  2. 제1항에 있어서, 상기 제1절연막과 제2절연막은 질화막으로 형성되는 것을 특징으로 하는 반도체 소자의 소자분리절연막 형성방법
  3. 제1항에 있어서, 상기 습식방법은 상기 수산화암모늄의 온도를 80 내지 100℃로 하고 식각시간을 10 내지 30분으로 하여 실시되는 것을 특징으로 하는 반도체 소자 소자분리절연막 형성방법
  4. 반도체기판 상부에 패드산화막 및 제1절연막을 형성하는 공정과, 상기 반도체기판의 비활성영역이 노출되는 제1절연막패턴을 형성하는 공정과, 상기 제1절연막 측벽에 제2절연막 스페이서를 형성하는 공정과, 상기 제1절연막패턴과 제2절연막 스페이서를 마스크로하여 상기 반도체기판을 일정두께 식각하여 트렌치를 형성하는 공정과, 상기 트렌치 형성공정시 발생되는 격자결함을 제거하기 위하여 상기 제1절연막패턴과 제2절연막 스페이서를 마스크로하여 상기 트렌치의 표면에 게르마늄 불순물을 일정농도, 일정에너지로 주입함으로써 비정질화된 여역을 형성하는 공정과, 상기 비정질화된 영역을 SPE 공정을 실시하여 결정화시키는 공정과, 열산화공정으로 상기 트렌치에 소자분리절연막을 형성하는 공정을 포함하는 반도체 소자의 소자분리절연막 형성방법
  5. 제4항에 있어서, 상기 제1절연막과 제2절연막은 질화막으로 형성되는 것을 특징으로 하는 반도체 소자의 소자분리절연막 형성방법
  6. 제4항에 있어서, 상기 일정농도는 9×1013/㎠ 내지 1.0×1015/㎠ 농도인 것을 특징으로 하는 반도체 소자의 소자분리절연막 형성방법
  7. 제4항에 있어서, 상기 일정에너지는 10 내지 100 KeV의 에너지인 것을 특징으로 하는 반도체 소자의 소자분리절연막 형성방법
  8. 제4항에 있어서, 상기 SPE 공정은 질소가스분위기, 500 내지 600℃ 온도에서 1 내지 3시간동안 열처리되는 것을 특징으로 하는 반도체 소자의 소자분리절연막 형성방법
KR1019950026729A 1995-08-26 1995-08-26 반도체소자의 소자분리 절연막 형성방법 KR100197648B1 (ko)

Priority Applications (3)

Application Number Priority Date Filing Date Title
KR1019950026729A KR100197648B1 (ko) 1995-08-26 1995-08-26 반도체소자의 소자분리 절연막 형성방법
US08/702,062 US5637529A (en) 1995-08-26 1996-08-23 Method for forming element isolation insulating film of semiconductor device
JP8240974A JP2682529B2 (ja) 1995-08-26 1996-08-26 半導体素子の素子分離絶縁膜形成方法

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KR1019950026729A KR100197648B1 (ko) 1995-08-26 1995-08-26 반도체소자의 소자분리 절연막 형성방법

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KR970013198A true KR970013198A (ko) 1997-03-29
KR100197648B1 KR100197648B1 (ko) 1999-06-15

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JP (1) JP2682529B2 (ko)
KR (1) KR100197648B1 (ko)

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KR100470160B1 (ko) * 1998-12-30 2005-04-06 주식회사 하이닉스반도체 반도체 소자의 소자분리막 형성 방법
KR100770455B1 (ko) * 2001-06-22 2007-10-26 매그나칩 반도체 유한회사 반도체소자의 제조방법

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KR100211547B1 (ko) * 1996-10-29 1999-08-02 김영환 반도체 소자의 필드 산화막 형성방법
KR100232887B1 (ko) * 1996-12-20 1999-12-01 김영환 필드 산화막 제조방법
JP2956635B2 (ja) * 1997-02-04 1999-10-04 日本電気株式会社 半導体装置およびその製造方法
KR100235950B1 (ko) * 1997-06-26 1999-12-15 김영환 반도체 소자의 필드 산화막 제조방법
WO1999025018A1 (en) * 1997-11-07 1999-05-20 Advanced Micro Devices, Inc. Semiconductor device having an improved isolation region and process of fabrication thereof
US5915195A (en) * 1997-11-25 1999-06-22 Advanced Micro Devices, Inc. Ion implantation process to improve the gate oxide quality at the edge of a shallow trench isolation structure
KR100480231B1 (ko) * 1998-10-07 2005-06-08 주식회사 하이닉스반도체 반도체장치의 필드 산화막 형성방법
US6165871A (en) * 1999-07-16 2000-12-26 Chartered Semiconductor Manufacturing Ltd. Method of making low-leakage architecture for sub-0.18 μm salicided CMOS device
US6881645B2 (en) * 2000-08-17 2005-04-19 Samsung Electronics Co., Ltd. Method of preventing semiconductor layers from bending and semiconductor device formed thereby
FR2819631B1 (fr) * 2001-01-12 2003-04-04 St Microelectronics Sa Procede de fabrication d'un substrat monocristallin, et circuit integre comportant un tel substrat
KR100425998B1 (ko) * 2001-12-27 2004-04-06 동부전자 주식회사 실리콘 섭스트레이트의 소자 분리 방법
KR100444609B1 (ko) * 2002-10-30 2004-08-16 주식회사 하이닉스반도체 반도체 소자의 소자 분리막 형성 방법
US6902971B2 (en) * 2003-07-21 2005-06-07 Freescale Semiconductor, Inc. Transistor sidewall spacer stress modulation
US6917093B2 (en) * 2003-09-19 2005-07-12 Texas Instruments Incorporated Method to form shallow trench isolation with rounded upper corner for advanced semiconductor circuits
US9698044B2 (en) * 2011-12-01 2017-07-04 Taiwan Semiconductor Manufacturing Company, Ltd. Localized carrier lifetime reduction

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US5149669A (en) * 1987-03-06 1992-09-22 Seiko Instruments Inc. Method of forming an isolation region in a semiconductor device
US4986879A (en) * 1987-06-15 1991-01-22 Ncr Corporation Structure and process for forming semiconductor field oxide using a sealing sidewall of consumable nitride
US4728619A (en) * 1987-06-19 1988-03-01 Motorola, Inc. Field implant process for CMOS using germanium
US4920076A (en) * 1988-04-15 1990-04-24 The United States Of America As Represented By The United States Department Of Energy Method for enhancing growth of SiO2 in Si by the implantation of germanium
US5266510A (en) * 1990-08-09 1993-11-30 Micron Technology, Inc. High performance sub-micron p-channel transistor with germanium implant
US5298451A (en) * 1991-04-30 1994-03-29 Texas Instruments Incorporated Recessed and sidewall-sealed poly-buffered LOCOS isolation methods

Cited By (2)

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Publication number Priority date Publication date Assignee Title
KR100470160B1 (ko) * 1998-12-30 2005-04-06 주식회사 하이닉스반도체 반도체 소자의 소자분리막 형성 방법
KR100770455B1 (ko) * 2001-06-22 2007-10-26 매그나칩 반도체 유한회사 반도체소자의 제조방법

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JP2682529B2 (ja) 1997-11-26
JPH09106984A (ja) 1997-04-22
US5637529A (en) 1997-06-10
KR100197648B1 (ko) 1999-06-15

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