KR970012068A

KR970012068A - System clock signal generation circuit

Info

Publication number: KR970012068A
Application number: KR1019950023671A
Authority: KR
Inventors: 김석진
Original assignee: 문정환; Lg 반도체주식회사
Priority date: 1995-08-01
Filing date: 1995-08-01
Publication date: 1997-03-29
Also published as: KR0167250B1

Abstract

본 발명은 시스템 클럭신호를 생성하는 기술에 관한 것으로, 주위의 온도나 전압변화에 관계없이 시스템클럭 신호간에 일정한 넌-오버래핑구간을 갖도록 하기 위하여, 콘트롤신호 출력부(300)를 통해 시스템클럭신호(SCK₁), (SCK₂)가 정상적인 넌-오버래핑구간을 갖지 못할 때, 소정의 제어신호(CS=L)를 출력하여 인위적으로 전송게이트(TR₁₂), (TR₁₄)를 온시킴으로써 지연기(11), (13)의 출력신호가 한번 더 지연기(12), (14)를 통해 지연출력되어 그 시스템클럭신호(SCK₁), (SCK₂)가 정상적인 넌-오버래핑구간을 갖도록 하였다.The present invention relates to a technique for generating a system clock signal, and in order to have a constant non-overlapping interval between system clock signals regardless of ambient temperature or voltage change, the system clock signal (through the control signal output unit 300) When SCK ₁ ) and (SCK ₂ ) do not have a normal non-overlapping interval, a delay control may be performed by outputting a predetermined control signal CS = L and artificially turning on the transfer gates TR ₁₂ and TR ₁₄ . 11), the output signals of (13) are delayed again through the delayers 12 and 14 so that the system clock signals SCK ₁ and SCK ₂ have normal non-overlapping intervals.

Description

System clock signal generation circuit

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 본 발명의 16비트 마이크로 프로세서와 실시간 클럭 인터페이스 장치의 회로도2 is a circuit diagram of a 16-bit microprocessor and a real time clock interface device of the present invention.

제3도는 본 발명의 실시간 클럭IC의 어드레스 맵도.3 is an address map diagram of a real time clock IC of the present invention.

Claims

The first clock signal generator 100 generates a clock signal S1 by NAND combining the source clock signal CKs and the source clock signal through the delayer, and the source clock signal through the inverted source clock signal and the inverter and the delayer. In the clock signal generation circuit composed of the second clock signal generation unit 200 which generates a clock signal S2 by NAND combining the signals, the non-overlapping interval between the system clock signals SCK ₁ and SCK ₂ is normal. Control signal output unit 300 that detects whether the signal is abnormal and outputs a control signal CS accordingly, and when the non-overlapping section between the system clock signals SCK ₁ and SCK ₂ is abnormally detected. The first delay unit 100A and the system clock signal outputting the second delayed signal again by the first clock signal generator 100 by using the transmission gate under the control of the signal output unit 300. Non-overlapping section between SCK ₁ ) and (SCK ₂ ) is abnormal When detected, the second delay unit 200A delays the first delayed signal from the second clock signal generator 200 again by using a transmission gate controlled by the control signal output unit 300 and outputs the second delayed signal. System clock signal generation circuit further comprises a.

And an inverter (I ₁₀₎ to the system clock signal (SCK ₂₎ via the control signal output unit 300, the inverting output, and a system clock signal (SCK ₁₎ as a control signal through the output signal of said inverter (I ₁₀₎ of three-state buffer (B _11), and the three-state buffer when it outputs a control signal (CS) when the normal pulse cycle received from the (B ₁₁₎ to "high", and the pulse of the abnormal cycle input "low" The system clock signal generation circuit, characterized in that consisting of a latch (10) for outputting.

※ Note: The disclosure is based on the initial application.