KR970008493A - Contact hole wiring method of optical path control device - Google Patents

Contact hole wiring method of optical path control device Download PDF

Info

Publication number
KR970008493A
KR970008493A KR1019950023349A KR19950023349A KR970008493A KR 970008493 A KR970008493 A KR 970008493A KR 1019950023349 A KR1019950023349 A KR 1019950023349A KR 19950023349 A KR19950023349 A KR 19950023349A KR 970008493 A KR970008493 A KR 970008493A
Authority
KR
South Korea
Prior art keywords
conductive layer
contact hole
insulating layer
optical path
path control
Prior art date
Application number
KR1019950023349A
Other languages
Korean (ko)
Other versions
KR0160892B1 (en
Inventor
민용기
Original Assignee
배순훈
대우전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 배순훈, 대우전자 주식회사 filed Critical 배순훈
Priority to KR1019950023349A priority Critical patent/KR0160892B1/en
Publication of KR970008493A publication Critical patent/KR970008493A/en
Application granted granted Critical
Publication of KR0160892B1 publication Critical patent/KR0160892B1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76814—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Mechanical Light Control Or Optical Switches (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

본 발명은 광로 조절 장치의 콘택홀을 통하여 패드와 작동 전극을 연결시키기 위한 방법을 개시한다. 본 발명은 구동 기판상에 형성된 제1절연층을 패터닝시켜서 콘택홀을 형성시키고 상기 제1절연층상에 도전체 금속을 적층시킨 후 일부를 식각시킨 제1도전층을 형성시키는 제1단계와, 상기 제1도전층상에 제2절연층과 제2도전층을 순차적으로 형성시키는 제2단계로 이루어지고 상기 제2절연층은 급가열 공정에 의하여 열처리되는 것을 특징으로 하는 광로 조절 장치의 콘택홀 배선 방법에 의해 달성되며 이에 의해서 도전층간의 전기적 쇼트 현상을 방지시키고 평탄한 표면을 제공하므로 광로 조절 장치의 성능을 향상시킬 수 있다.The present invention discloses a method for connecting a pad and a working electrode through a contact hole of an optical path control device. The present invention provides a first step of forming a contact hole by patterning a first insulating layer formed on a driving substrate, and forming a first conductive layer formed by etching a portion of the conductive metal by laminating a conductive metal on the first insulating layer; And a second step of sequentially forming a second insulating layer and a second conductive layer on the first conductive layer, wherein the second insulating layer is heat-treated by a rapid heating process. It is achieved by, thereby preventing the electrical short between the conductive layers and providing a flat surface, thereby improving the performance of the optical path control device.

Description

광로 조절 장치의 콘택홀 배선 방법Contact hole wiring method of optical path control device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도(가) 및 (나)는 본 발명에 따라서 광로 조절 장치를 제작하기 위한 공정도.2 (a) and (b) is a process chart for manufacturing the optical path control apparatus according to the present invention.

Claims (7)

구동 기판(110)상에 적층된 제1절연층(132)을 페터닝시킴으로서 형성된 콘택홀(140)을 통하여 패드(120)와전기적으로 연결되고 상기 제1절연층(132)상에 적층된 도전체 금속의 일부를 식각시켜서 제1도전층(210)을 형성시키는 제1단계와, 상기 제1도전층(210)상에 제2절연층(220)과 제2도전층(230)을 순차적으로 형성시키는 제2단계로 이루어진 것을특징으로 하는 광로 조절 장치의 콘택홀 배선 방법.A conductive layer electrically connected to the pad 120 through the contact hole 140 formed by patterning the first insulating layer 132 stacked on the driving substrate 110 and stacked on the first insulating layer 132. Etching a portion of the sieve metal to form the first conductive layer 210, and sequentially forming the second insulating layer 220 and the second conductive layer 230 on the first conductive layer 210. A contact hole wiring method of an optical path control apparatus characterized by comprising a second step of forming. 제1항에 있어서, 상기 제1도전층(210)은 상기 식각 공정에 의하여 상기 패드(120)와 전기적으로 단선되는 것을 특징으로 하는 광로 조절 장치의 콘택홀 배선 방법.The contact hole wiring method of claim 1, wherein the first conductive layer is electrically disconnected from the pad by the etching process. 제2항에 있어서, 상기 제1도전층(210)의 일부는 포토 리쏘그래픽 공정 또는 플라즈마 이온 식각 공정에 의하여 식각되는 것을 특징으로 하는 광로 조절 장치의 콘택홀 배선 방법.The method of claim 2, wherein a portion of the first conductive layer is etched by a photolithographic process or a plasma ion etching process. 제3항에 있어서, 상기 제2단계는 상기 제2절연층(220)의 일부를 식각시켜서 상기 제1도전층(210)의 일부를 노출시키는 공정을 포함하고 있는 것을 특징으로 하는 광로 조절 장치의 콘택홀 배선 방법.4. The optical path control apparatus of claim 3, wherein the second step includes etching a portion of the second insulating layer 220 to expose a portion of the first conductive layer 210. Contact hole wiring method. 제4항에 있어서, 상기 제2절연층(220)의 일부는 포토 리쏘그래픽 공정 또는 플라즈마 이온 식각 공정에 의하여 식각되는 것을 특징으로 하는 광로 조절 장치의 콘택홀 배선 방법.5. The method of claim 4, wherein a part of the second insulating layer is etched by a photolithography process or a plasma ion etching process. 6. 제5항에 있어서, 상기 제2도전층(230)은 상기 노출된 제1도전층(210)의 일부를 통하여 상기 패드(120)와 전기적으로 연결되어 있는 것을 특징으로 하는 광로 조절 장치의 콘택홀 배선 방법.The contact hole of claim 5, wherein the second conductive layer 230 is electrically connected to the pad 120 through a portion of the exposed first conductive layer 210. Wiring method. 제6항에 있어서, 상기 제2절연층(220)은 급가열 공정에 의하여 열처리되는 것을 특징으로 하는 광로 조절장치의 콘택홀 배선 방법.7. The method of claim 6, wherein the second insulating layer is heat treated by a rapid heating process. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950023349A 1995-07-31 1995-07-31 Method for conductor through a control hall of the otpcial projection system KR0160892B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950023349A KR0160892B1 (en) 1995-07-31 1995-07-31 Method for conductor through a control hall of the otpcial projection system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950023349A KR0160892B1 (en) 1995-07-31 1995-07-31 Method for conductor through a control hall of the otpcial projection system

Publications (2)

Publication Number Publication Date
KR970008493A true KR970008493A (en) 1997-02-24
KR0160892B1 KR0160892B1 (en) 1999-02-01

Family

ID=19422340

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950023349A KR0160892B1 (en) 1995-07-31 1995-07-31 Method for conductor through a control hall of the otpcial projection system

Country Status (1)

Country Link
KR (1) KR0160892B1 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102493831B1 (en) 2021-03-04 2023-01-31 주식회사 에이텍에이피 Apparatus for receiving and dispensing of medium
KR102493855B1 (en) 2021-03-04 2023-01-31 주식회사 에이텍에이피 Control method of medium receiving and dispensing apparatus

Also Published As

Publication number Publication date
KR0160892B1 (en) 1999-02-01

Similar Documents

Publication Publication Date Title
TW200508417A (en) Method for contacting conducting layers overlying magnetoelectronic elements of mram devices
KR950004455A (en) Semiconductor device and manufacturing method thereof
KR950001901A (en) Contact hole manufacturing method
KR940010197A (en) Manufacturing Method of Semiconductor Device
KR940022801A (en) Contact formation method of semiconductor device
KR970008493A (en) Contact hole wiring method of optical path control device
KR970008408A (en) Multilayer wiring flattening method of optical path control device
KR970008356A (en) Contact hole wiring method of optical path control device
KR0149889B1 (en) Field effect device and method for forming electrodes of the same
KR970012960A (en) Contact hole wiring method of optical path control device
KR970008492A (en) Multilayer wiring flattening method of optical path control device
KR940027100A (en) Method for forming multilayer wiring of semiconductor device
KR970054008A (en) Capacitor Manufacturing Method of Semiconductor Device
KR970054004A (en) Bit line formation method of semiconductor device
KR970054076A (en) Capacitor of Semiconductor Device and Manufacturing Method Thereof
KR970018216A (en) Planarization Method of Semiconductor Device
KR970052231A (en) Contact hole formation method of semiconductor device
KR960026191A (en) Metal wiring formation method of semiconductor device
KR970018074A (en) Wiring Formation Method of Semiconductor Device
KR940012572A (en) Contact Forming Method in Semiconductor Device
KR970052318A (en) Method for forming contact layer of semiconductor device
TW354418B (en) A method for preventing the increasing of a un-grounding contact window resistance
KR970052248A (en) Contact hole formation method of semiconductor device
KR950021414A (en) Connecting process between multilayer wirings of semiconductor device
KR930022473A (en) Manufacturing method of semiconductor device having multilayer wiring structure

Legal Events

Date Code Title Description
A201 Request for examination
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20060704

Year of fee payment: 9

LAPS Lapse due to unpaid annual fee