KR970004030A - Method for manufacturing nonvolatile semiconductor memory device - Google Patents

Method for manufacturing nonvolatile semiconductor memory device Download PDF

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KR970004030A
KR970004030A KR1019950015595A KR19950015595A KR970004030A KR 970004030 A KR970004030 A KR 970004030A KR 1019950015595 A KR1019950015595 A KR 1019950015595A KR 19950015595 A KR19950015595 A KR 19950015595A KR 970004030 A KR970004030 A KR 970004030A
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impurity
impurity region
conductive
forming
photoresist pattern
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KR1019950015595A
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KR0147649B1 (en
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최용주
김장래
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김광호
삼성전자 주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274—Photolithographic processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
    • H01L29/7881—Programmable transistors with only two possible levels of programmation
    • H01L29/7884—Programmable transistors with only two possible levels of programmation charging by hot carrier injection

Abstract

불휘발성 반도체 메모리 장치의 제조방법에 관하여 개시한다. 그 내부에 제1도전형의 제2불순물 영역이 형성되어 있는 제1불순물 영역상에 게이트 산화막을 형성하고, 도전물을 증착하여 저전압 및 고전압 소자의 게이트 도전층을 형성한 다음,상기 결과물 상에 제1포토레지스트 패턴을 형성하고, 고전압 소자의 소오스/드레인 형성을 위한 저농도 제2도전형 불순물을 이온주입한다. 이어서, 상기 제1포토레지스트 패턴을 제거하고, 상기 결과물 상에 절연물을 증착하고 에치백하여 스페이서를 형성하고, 제2포토레지스트 패턴을 형성한 다음, 저전압 소자의 소오스/드레인 형성을 위한 저농도 제2도전형의 불순물을 반도체 기판에 대해 일정각도로 이온주입하고, 고전압 및 저전압 소자의 소오스/드레인 형성을 위한 고농도제2도전형의 불순물을 상기 기판에 통상의 방법으로 이온주입한다. 따라서, 고전압 소자의 소오스/드레인을 형성하기 위한 기존의 공정보다 1장의 마스크를 감소시킬 수 있으며, 저전압 소자의 LDD구조를 마스크의 추가 사용없이 형성할 수 있다.A method of manufacturing a nonvolatile semiconductor memory device is disclosed. A gate oxide film is formed on the first impurity region in which the second impurity region of the first conductivity type is formed, a conductive material is deposited to form a gate conductive layer of a low voltage and a high voltage device, and then on the resultant. A first photoresist pattern is formed, and ion implanted with low concentration second conductive impurity for source / drain formation of the high voltage device. Subsequently, the first photoresist pattern is removed, an insulator is deposited and etched back on the resultant to form a spacer, a second photoresist pattern is formed, and a second low concentration for source / drain formation of the low voltage device. A conductive impurity is implanted at an angle to the semiconductor substrate, and a high concentration second conductive impurity is implanted into the substrate in a conventional manner for source / drain formation of high voltage and low voltage devices. Therefore, one mask can be reduced compared to the conventional process for forming the source / drain of the high voltage device, and the LDD structure of the low voltage device can be formed without additional use of the mask.

Description

불휘발성 반도체 메모리 장치 제조방법Method for manufacturing nonvolatile semiconductor memory device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제3G도는 본 발명의 일 실시예에 의ㅎ나 불휘발성 메모리 장치 제조방법을 설명하기 위한 공정순서도.3G is a process flowchart illustrating a method of manufacturing a nonvolatile memory device according to an embodiment of the present invention.

Claims (12)

그 내부에 제1도전형의 제2불순물 영역이 형성되어 있는 제1불순물 영역 상에 게이트 산화막을 형성하는단계; 게이트 산화막이 형성되어 있는 상기 결과물 상에 도전물을 증착한 다음 패터닝하여 저전압 및 고전압 소자의 게이트 도전층을 형성하는 단계; 사진 공정을 이용하여 상기 결과물 상에 제1포토레지스트 패턴을 형성하는 단계; 상기 제1포토레지스트 패턴을 이온주입 마스크로 사용하여 고전압 소자의 소오스/드레인 형성을 위한 저농도 제2도전형 불순물을 이온주입하는 단계; 상기 제1 포토레지스트 패턴을 제거하는 단계; 상기 결과물 상에 절연물을 증착하고 에치백하여 상기게이트 도전층 측벽에 스페이서를 형성하는 단계; 스페이서가 형성된 상기 결과물 상에 제2포토레지스트 패턴을 형성하는 단계; 상기 제2포토레지스트 패턴을 이온주입 마스크로 사용하여 저전압 소자의 소오스/드레인 형성을 위한 저농도 제2도전형의 불순물을 반도체 기판에 대해 일정각도로 이온주입한 다음, 고전압 및 저전압 소자의 소오스/드레인 형성을 위한 고농도 제2도전형 불순물을 상기 기판에 통상의 방법으로 이온주입하는 단계를 구비하는 것을 특징으로 하는 불휘발성 반도체 메모리 장치의 제조방법.Forming a gate oxide film on the first impurity region in which the second impurity region of the first conductivity type is formed; Depositing a conductive material on the resultant having the gate oxide film formed thereon and patterning the conductive material to form a gate conductive layer of a low voltage and a high voltage device; Forming a first photoresist pattern on the resultant using a photo process; Ion implanting a low concentration second conductive impurity for source / drain formation of a high voltage device using the first photoresist pattern as an ion implantation mask; Removing the first photoresist pattern; Depositing and etching back an insulator on the resultant to form spacers on sidewalls of the gate conductive layer; Forming a second photoresist pattern on the resultant formed spacers; The second photoresist pattern is used as an ion implantation mask to implant a low-concentration second conductivity type impurity to form a source / drain of a low voltage device at a predetermined angle with respect to the semiconductor substrate, and then to source / drain the high and low voltage devices. A method of manufacturing a nonvolatile semiconductor memory device comprising the step of ion implanting a high concentration second conductivity type impurity for formation into the substrate in a conventional manner. 제1항에 있어서, 상기 게이트산화막을 형성하는 단계는, 제1도전형의 제1불순물 영역에 제1도전형의 제2불순물 영역을 형성하는 단계; 제2불순물 영역이 형성된 상기 결과물 상에 소자분리를 위한 필드산화막을 형성하는 단계;상기 제1불순물 영역의 트랜지스터 문턱전압을 조절하기 위해 제1도전형의 불순물을 이온주입하는 단계; 상기 결과물 상에 제1게이트 산화막을 형성하는 단계; 사진식각 공정을 이용하여 제2불순물 영역 상부의 상기 제1게이트 산화막을 제거하는 단계; 상기 제2불순물 영역의 트랜지스터 문턱전압을 조절하기 위해 제1도전형의 불순물을 이온주입하는 단계; 및상기 결과물 상에 제2게이트 산화막을 형성하는 단계를 구비하는 것을 특징으로 하는 불휘발성 반도체 메모리 장치의 제조방법.The method of claim 1, wherein the forming of the gate oxide film comprises: forming a second impurity region of a first conductivity type in a first impurity region of a first conductivity type; Forming a field oxide film for device isolation on the resultant product having a second impurity region; ion implanting impurities of a first conductivity type to control a transistor threshold voltage of the first impurity region; Forming a first gate oxide film on the resultant product; Removing the first gate oxide layer on the second impurity region using a photolithography process; Implanting impurities of a first conductivity type to adjust the transistor threshold voltage of the second impurity region; And forming a second gate oxide layer on the resultant material. 제2항에 있어서, 상기 제1불순물 영역 상부의 게이트 산화막이 상기 제2불순물 영역 상부의 게이트 산화막보다 더 두꺼운 것을 특징으로 하는 불휘발성 반도체 메모리 장치의 제조방법.The method of claim 2, wherein the gate oxide layer on the first impurity region is thicker than the gate oxide layer on the second impurity region. 제1항에 있어서, 상기 제1불순물 영역은 반도체 기판이고, 상기 제2불순물 영역은 웰인 것을 특징으로 하는 불휘발성 반도체 메모리 장치의 제조방법.The method of claim 1, wherein the first impurity region is a semiconductor substrate and the second impurity region is a well. 제1항에 있어서, 상기 제1불순물 영역에는 고전압 소자를 형성하고, 상기 제2불순물 영역에는 저전압 소자를 형성하는 것을 특징으로 하는 불휘발성 반도체 메모리 장치의 제조방법.The method of claim 1, wherein a high voltage device is formed in the first impurity region, and a low voltage device is formed in the second impurity region. 제1항에 있어서, 상기 제1도전형의 불순물은 P형이고, 제2도전형의 불순물은 N형인 것을 특징으로 하는 불휘발성 반도체 메모리 장치의 제조방법.The method of manufacturing a nonvolatile semiconductor memory device according to claim 1, wherein the impurity of the first conductive type is P type and the impurity of the second conductive type is N type. 제1항 또는 제6항에 있어서, 상기 저농도 불순물로 인(P)을 사용하고, 고농도 불순물로 비소(As)를 사용하는 것을 특징으로 하는 불휘발성 반도체 메모리 장치의 제조방법.The method of manufacturing a nonvolatile semiconductor memory device according to claim 1 or 6, wherein phosphorus (P) is used as the low concentration impurity and arsenic (As) is used as the high concentration impurity. 제1항에 있어서, 상기 저농도 불순물 이온주입과 고농도 불순물 이온주입이 연속하여 이루어지는 것을 특징으로 하는 불휘발성 반도체 메모리 장치의 제조방법.The method of manufacturing a nonvolatile semiconductor memory device according to claim 1, wherein the low concentration impurity ion implantation and the high concentration impurity ion implantation are successively performed. 제1항에 있어서, 상기 제2도전형의 고농도 및 저농도 불순물의 농도차이가 103~107atoms/㎤인 것을 특징으로 하는 불휘발성 반도체 메모리 장치의 제조방법.The method of manufacturing a nonvolatile semiconductor memory device according to claim 1, wherein the concentration difference between the high concentration and the low concentration impurity of the second conductive type is 10 3 to 10 7 atoms / cm 3. 제1항에 있어서, 상기 제2포토레지스트 패턴은 상기 제1불순물 영역의 게이트 도전층 상부 및 상기 게이트 도전층으로부터 일정거리 이격된 영역을 포함하는 영역 상부에 형성된 것을 특징으로 하는 불휘발성 반도체 메모리 장치의 제조방법.The nonvolatile semiconductor memory device of claim 1, wherein the second photoresist pattern is formed on the gate conductive layer of the first impurity region and on the region including a region spaced a predetermined distance from the gate conductive layer. Manufacturing method. 제10항에 있어서, 상기 일정거리는 0.3㎛∼1.0㎛인 것을 특징으로 하는 불휘발성 반도체 메모리 장치의 제조방법.The method of claim 10, wherein the predetermined distance is 0.3 μm to 1.0 μm. 제1항에 있어서, 상기 제2도전형 불순물 이온주입시 기판에 대한 일정각도는 15도∼60도인 것을 특징으로하는 불휘발성 반도체 메모리 장치의 제조방법.The method of claim 1, wherein a predetermined angle with respect to the substrate when the second conductive impurity ion is implanted is 15 degrees to 60 degrees. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950015595A 1995-06-13 1995-06-13 Method of fabricating a non-volatile memory device KR0147649B1 (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20010090627A (en) * 2000-04-10 2001-10-19 이관철 Shoes containing the inline roller and the converting device thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20010090627A (en) * 2000-04-10 2001-10-19 이관철 Shoes containing the inline roller and the converting device thereof

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