KR970003892B1 - Method of isolation of the elements on the semiconductor device - Google Patents
Method of isolation of the elements on the semiconductor device Download PDFInfo
- Publication number
- KR970003892B1 KR970003892B1 KR93020623A KR930020623A KR970003892B1 KR 970003892 B1 KR970003892 B1 KR 970003892B1 KR 93020623 A KR93020623 A KR 93020623A KR 930020623 A KR930020623 A KR 930020623A KR 970003892 B1 KR970003892 B1 KR 970003892B1
- Authority
- KR
- South Korea
- Prior art keywords
- layer
- oxide layer
- silicon
- polysilicon
- silicon layer
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Element Separation (AREA)
- Bipolar Transistors (AREA)
Abstract
An element separation method of a semiconductor device reduces a oxidation time and oxidation temperature in an element separation process of a bipolar element, and minimizes an up-phenomenon of a buried layer. The method includes the steps of: forming an epitaxial layer(3) on a semiconductor substrate(1); forming a first oxide layer(4) and a first silicon layer(5) on the epitaxial layer(3); patterning the first silicon layer(5) and the first oxide layer(4); etching the epitaxial layer(3) by using the first silicon layer(5) and the first oxide layer(4) as a mask; sequentially forming a second oxide layer(6), a polysilicon layer(10), a second silicon layer(7) and CVD oxide layer(8); etching back the CVD oxide layer(8) in order to make a surface of the polysilicon be exposed; selectively removing the second silicon layer(7); removing a remaining CVD oxide layer(8); performing an ion implantation with a high dose impurity about the polysilicon layer(10); forming an element separation oxide layer(9) on a predetermined area; and removing the remaining second silicon layer(7), polysilicon layer(10), first silicon layer(5) and the first oxide layer(4).
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR93020623A KR970003892B1 (en) | 1993-10-06 | 1993-10-06 | Method of isolation of the elements on the semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR93020623A KR970003892B1 (en) | 1993-10-06 | 1993-10-06 | Method of isolation of the elements on the semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
KR950012676A KR950012676A (en) | 1995-05-16 |
KR970003892B1 true KR970003892B1 (en) | 1997-03-22 |
Family
ID=19365320
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR93020623A KR970003892B1 (en) | 1993-10-06 | 1993-10-06 | Method of isolation of the elements on the semiconductor device |
Country Status (1)
Country | Link |
---|---|
KR (1) | KR970003892B1 (en) |
-
1993
- 1993-10-06 KR KR93020623A patent/KR970003892B1/en not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
KR950012676A (en) | 1995-05-16 |
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Payment date: 20050221 Year of fee payment: 9 |
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