KR970003819A - Semiconductor manufacturing method - Google Patents

Semiconductor manufacturing method Download PDF

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Publication number
KR970003819A
KR970003819A KR1019950019090A KR19950019090A KR970003819A KR 970003819 A KR970003819 A KR 970003819A KR 1019950019090 A KR1019950019090 A KR 1019950019090A KR 19950019090 A KR19950019090 A KR 19950019090A KR 970003819 A KR970003819 A KR 970003819A
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KR
South Korea
Prior art keywords
solution
semiconductor manufacturing
wet etching
semiconductor
etching
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KR1019950019090A
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Korean (ko)
Inventor
윤용혁
이병석
김상욱
Original Assignee
김주용
현대전자산업 주식회사
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Application filed by 김주용, 현대전자산업 주식회사 filed Critical 김주용
Priority to KR1019950019090A priority Critical patent/KR970003819A/en
Publication of KR970003819A publication Critical patent/KR970003819A/en

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Abstract

본 발명은 PBL(Polysilicon Buffered LOCOS) 공정중 완충막으로 사용되는 폴리실리콘막을 하부층인 패드산화막과의 식각선택비가 50:1이상인 용액에서 습식식각으로 제거하는 것을 특징으로 하는 반도체 제조 방법에 관한 것으로, 폴리실리콘막을 제거할 때 하부층인 패드산화막에 전혀 손상을 주지 않고, 또한 반도체 기판에도 손상을 주지 않는 식각방법을 사용하므로써, 반도체 소자의 신뢰도 및 수율을 향상시키는 효과가 있다.The present invention relates to a method for manufacturing a semiconductor, characterized in that the polysilicon film used as a buffer film during the PBL process is removed by wet etching in a solution having an etching selectivity of 50: 1 or more with a pad oxide film as a lower layer. When the polysilicon film is removed, by using an etching method that does not damage the pad oxide film, which is the underlying layer, and does not damage the semiconductor substrate, there is an effect of improving the reliability and yield of the semiconductor device.

Description

반도체 제조 방법Semiconductor manufacturing method

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2A도 내지 제2C도는 본 발명의 일실시예에 따른 PBL 구조의 소자분리막 형성 공정도.2A to 2C are diagrams illustrating a process of forming a device isolation film having a PBL structure according to an embodiment of the present invention.

Claims (3)

반도체 제조 방법에 있어서; PBL(Polysilicon Buffered LOCOS) 공정중 완충막으로 사용되는 폴리실리콘막을 하부층인 패드 산화막과의 식각선택비가 50:1이상인 용액에서 습식식각으로 제거하는 것을 특징으로 하는 반도체 제조 방법.A semiconductor manufacturing method; A method for fabricating a semiconductor, characterized in that the polysilicon film used as a buffer film during a PBL (Polysilicon Buffered LOCOS) process is removed by wet etching from a solution having an etching selectivity of 50: 1 or more with a pad oxide film as a lower layer. 제1항에 있어서, 상기 습식식각 용액은 암모니아수 및 순수용액의 혼합액인 것을 특징으로 하는 반도체 제조 방법.The method of claim 1, wherein the wet etching solution is a mixed solution of ammonia water and a pure solution. 제2항에 있어서; 상기 습식식각은 45℃내지 100℃온도에서 이루어지는 것을 특징으로 하는 반도체 제조 방법.The method of claim 2; The wet etching is a semiconductor manufacturing method, characterized in that at 45 ℃ to 100 ℃ temperature. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950019090A 1995-06-30 1995-06-30 Semiconductor manufacturing method KR970003819A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950019090A KR970003819A (en) 1995-06-30 1995-06-30 Semiconductor manufacturing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950019090A KR970003819A (en) 1995-06-30 1995-06-30 Semiconductor manufacturing method

Publications (1)

Publication Number Publication Date
KR970003819A true KR970003819A (en) 1997-01-29

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950019090A KR970003819A (en) 1995-06-30 1995-06-30 Semiconductor manufacturing method

Country Status (1)

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KR (1) KR970003819A (en)

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