KR970003617A - Method of forming planarization layer of semiconductor device - Google Patents

Method of forming planarization layer of semiconductor device Download PDF

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Publication number
KR970003617A
KR970003617A KR1019950016035A KR19950016035A KR970003617A KR 970003617 A KR970003617 A KR 970003617A KR 1019950016035 A KR1019950016035 A KR 1019950016035A KR 19950016035 A KR19950016035 A KR 19950016035A KR 970003617 A KR970003617 A KR 970003617A
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KR
South Korea
Prior art keywords
semiconductor device
forming
insulating film
planarization layer
impurity regions
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Application number
KR1019950016035A
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Korean (ko)
Other versions
KR100329608B1 (en
Inventor
이석규
Original Assignee
김주용
현대전자산업 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 김주용, 현대전자산업 주식회사 filed Critical 김주용
Priority to KR1019950016035A priority Critical patent/KR100329608B1/en
Publication of KR970003617A publication Critical patent/KR970003617A/en
Application granted granted Critical
Publication of KR100329608B1 publication Critical patent/KR100329608B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H01L21/02129—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being boron or phosphorus doped silicon oxides, e.g. BPSG, BSG or PSG

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Formation Of Insulating Films (AREA)

Abstract

본 발명은 반도체소자의 평탄화층 형성방법에 관한 것으로, 반도체 기판 상부에 물질층을 형성하고 그 상부에 플로우가 잘되는 절연막을 일정두께 형성한 다음, 상기 절연막 표면에 고농도의 불순물영역을 형성하고 고온 어닐링공정으로 상기 절연막을 플로우시킴으로써 결정 결함이 없는 평탄화층을 형성하여 반도체소자의 수율 및 신뢰성을 향상시키고 반도체소자의 고집적화를 가능하게 하는 기술이다.The present invention relates to a method of forming a planarization layer of a semiconductor device, wherein a material layer is formed on a semiconductor substrate, and an insulating film having a good flow thereon is formed to a predetermined thickness, and then a high concentration of impurity regions are formed on the surface of the insulating film, and high temperature annealing is performed. By flowing the insulating film in a process, a flattening layer free of crystal defects is formed to improve the yield and reliability of the semiconductor device and to enable high integration of the semiconductor device.

Description

반도체소자의 평탄화층 형성방법Method of forming planarization layer of semiconductor device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2A도 내지 제2C도는 본 발명의 실시예에 따른 반도체소자의 평탄화층 형성방법을 도시한 단면도.2A to 2C are cross-sectional views showing a method for forming a planarization layer of a semiconductor device according to an embodiment of the present invention.

Claims (5)

반도체 기판 상부에 물질층을 형성하는 공정과, 상기 물질층 상부에 절연막을 일정두께 형성하는 공정과, 상기 절연막의 표면에 고농도의 불순물영역을 형성하는 공정과, 고온 어닐링공정을 실시하여 상기 절연막을 플로우시킴으로써 평탄화층을 형성하는 공정을 포함하는 반도체소자의 평탄화층 형성방법.Forming a material layer on the semiconductor substrate, forming a predetermined thickness of the insulating film on the material layer, forming a high concentration of impurity regions on the surface of the insulating film, and performing a high temperature annealing process. A method of forming a planarization layer of a semiconductor device comprising the step of forming a planarization layer by flowing. 제1항에 있어서, 상기 절연막은 BPSG 산화막과 같이 플로우가 잘되는 절연물질인 것을 특징으로 하는 반도체소자의 평탄화층 형성방법.The method of claim 1, wherein the insulating film is an insulating material that flows well, such as a BPSG oxide film. 제2항에 있어서, 상기 BPSG 산화막은 상기 BPSG 산화막 내부에 함유된 B와 P의 농도가 2 내지 15%로 형성되는 것을 특징으로 하는 반도체소자의 평탄화층 형성방법.The method of claim 2, wherein the BPSG oxide film is formed at a concentration of 2 to 15% of B and P contained in the BPSG oxide film. 제1항에 있어서, 상기 고농도의 불순물영역은 붕소, 인, 비소, 실리콘 및게르마늄으로 이루어지는 군에서 한가지가 사용되는 것을 특징으로 하는 반도체소자의 평탄화층 형성방법.The method of claim 1, wherein one of the high concentration impurity regions is selected from the group consisting of boron, phosphorus, arsenic, silicon, and germanium. 제1항에 있어서, 상기 고온 어닐링공정은 700 내지 900℃에서 실시되는 것을 특징으로 하는 반도체소자의 평탄화층 형성방법.The method of claim 1, wherein the high temperature annealing process is performed at 700 to 900 ° C. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950016035A 1995-06-16 1995-06-16 Method for forming planarization layer in semiconductor device KR100329608B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950016035A KR100329608B1 (en) 1995-06-16 1995-06-16 Method for forming planarization layer in semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950016035A KR100329608B1 (en) 1995-06-16 1995-06-16 Method for forming planarization layer in semiconductor device

Publications (2)

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KR970003617A true KR970003617A (en) 1997-01-28
KR100329608B1 KR100329608B1 (en) 2002-10-31

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KR1019950016035A KR100329608B1 (en) 1995-06-16 1995-06-16 Method for forming planarization layer in semiconductor device

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Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63260050A (en) * 1987-04-16 1988-10-27 Ricoh Co Ltd Manufacture of semiconductor device
JP2535909B2 (en) * 1987-05-21 1996-09-18 ソニー株式会社 Wiring formation method
JPH03114219A (en) * 1989-04-28 1991-05-15 Fujitsu Ltd Manufacture of substrate for semiconductor device
KR930009548B1 (en) * 1990-11-08 1993-10-06 삼성전자 주식회사 Planarizing method of semiconductor device using doping process

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