KR960701398A - 프로세서 시스템 및 디버그모드 실현방법 - Google Patents

프로세서 시스템 및 디버그모드 실현방법 Download PDF

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KR960701398A
KR960701398A KR1019950703428A KR19950703428A KR960701398A KR 960701398 A KR960701398 A KR 960701398A KR 1019950703428 A KR1019950703428 A KR 1019950703428A KR 19950703428 A KR19950703428 A KR 19950703428A KR 960701398 A KR960701398 A KR 960701398A
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floating
point
normal
exception
mode
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KR1019950703428A
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KR0175115B1 (ko
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죠셉 피 브라트
죤 브레난
피터 얀 텍 히스
챤드라 에스 죠시
웰리암 에이 하프만
모니카 알. 노활
파울 로드만
죠셉 티 스캔론
맨 키트 탕
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윌리엄 더블유. 켈리
실리콘 그래픽스 인코오포레이티드
타쉬로 요시꾸니
가부시끼가이샤 도시바
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/36—Preventing errors by testing or debugging software
    • G06F11/3664—Environments for testing or debugging software
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3838—Dependency mechanisms, e.g. register scoreboarding
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3854—Instruction completion, e.g. retiring, committing or graduating
    • G06F9/3858—Result writeback, i.e. updating the architectural state or memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3861—Recovery, e.g. branch miss-prediction, exception handling
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3867—Concurrent instruction execution, e.g. pipeline, look ahead using instruction pipelines
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units

Abstract

정규부동소소점예외 없는 통상동작모드의 정규동소수점 예외 이는 디버그로드로 전환할 수 있는 프로세서 시스템. 이 프로세서 시스템은 정수와 부동소수점 명령을 디스패치하는 수단과, 정수명령을 실행하는 멀티스테이지 정수 파이프라인을 갖춘 정수유닛과, 부동소수점명령을 실행하는 멀티스테이지 부동소수점 파이프라인을 갖춘 부동소수점유닛과, 시스템을 통상동작모드와 디버그동작모드로 전환하는 수단을 갖춘다. 시스템이 디버그모그에 있을때 부동소수점 명령이 디스패치되고 나서붙 시스템이 상기 부동소수점명령이 예외를 일으키는 가의 여부를 판정할 때까지 명령이 처리되지 않도록 하고, 통상모드에 있지 않을 때 시스템이 정규예외를 송신할 수 있도록 한다.

Description

프로세서 시스템 및 디버그모드 실현방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명에 의한 프로세서 시스템(100)의 고레벨 대표 브록도이다,
제4도는 본 발명에 의한 전환동작의 대표 플로챠트이다.

Claims (4)

  1. 정규부동소수점예외 없는 통상동작모드와, 디버그동작모드로 전환할 수 있는 프로세서 시스템으로서, 정수 및 부동소수점명령을 디스패치하는 수단과, 상기 정수명령을 실행하는 멀티스테이지 정수 파이프라인을 갖춘, 상기 디스패치수단에 연결된 정수유닛과, 상기 부동소수점명령을 실행하는 멀티스테이지 부동소수점 파이프라인을 갖춘, 상기 디스패치수단과 상기 정수유닛에 연결된 부동소수점유닛과, 시스템을 통상동작모드와 디버그동작모드에 있을 때는 부동소수점명령이 디스패치되고 나서부터 시스템이 상기 부동소수점명령이 예외를 일으키는가의 여부를 판정할 때까지 명령이 처리되는 것을 방지하고, 통상모드에 있지 않을 때 시스템이 정규에외를 송신할 수 있도록 하는 상기 디스패치수단에 연결된 수단을 갖춘 프로세서 시스템.
  2. 제1항에 있어서, 상기 디스패치수단이 상기 부동소수점명령이 예외를 일으키는가의 여부를 시스템이 판정하는 것보다, 1개 이상앞의 부동소수점 파이프라인 스테이지에서 다시 명령을 디스패치하기 시작하는 프로세서 시스템.
  3. 디버그모드로 프로세서 시스템을 작동시키는 방법으로서, 정규부동소수점예외 없는 통상모드의 디버그모드 사이에서 시스템을 전환 할 수 있는 방법에 있어서, 시스템이 디버그모드로 전환했는가의 여부를 판정하는 단계와, 부동소수점명령을 디스패치하는 단계와, 시스템을 통상동작모드와 디버그동작모드 사이에서 전환하여, 시스템이 디버그모드에 있을 때는 부동소수점명령이 디스패치되고 나서부터 시스템이 상기 부동소수점명령이 예외를 일으키는가의 여부를 판정할 때까지 명령이 처리되지 않도록 하고, 통상모드에 있지 않을 때 시스템이 정규예외를 송신할 수 있도록 하는 단계로 된 방법.
  4. 제3항에 있어서, 상기 부동소수점명령이 예외를 일으켰는가의 엽를 시스템이 판정하는 것보다, 1개 또는 복수 사이클전에 다시 명령을 디스패치하는 단계를 갖춘 방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019950703428A 1993-12-15 1994-12-15 프로세서 시스템 및 디버그모드 실현방법 KR0175115B1 (ko)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US8/166969 1993-12-15
US08/166,969 1993-12-15
US08/166,969 US5537538A (en) 1993-12-15 1993-12-15 Debug mode for a superscalar RISC processor
PCT/JP1994/002110 WO1995016953A1 (fr) 1993-12-15 1994-12-15 Systeme informatique et modalites de passage en mode mise au point

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Publication Number Publication Date
KR960701398A true KR960701398A (ko) 1996-02-24
KR0175115B1 KR0175115B1 (ko) 1999-04-01

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Country Link
US (1) US5537538A (ko)
EP (1) EP0684552B1 (ko)
JP (1) JP2843152B2 (ko)
KR (1) KR0175115B1 (ko)
CN (1) CN1084496C (ko)
DE (1) DE69428110T2 (ko)
HK (1) HK1018167A1 (ko)
TW (1) TW274595B (ko)
WO (1) WO1995016953A1 (ko)

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Publication number Publication date
DE69428110T2 (de) 2002-04-25
US5537538A (en) 1996-07-16
TW274595B (ko) 1996-04-21
EP0684552B1 (en) 2001-08-29
EP0684552A1 (en) 1995-11-29
KR0175115B1 (ko) 1999-04-01
WO1995016953A1 (fr) 1995-06-22
JP2843152B2 (ja) 1999-01-06
DE69428110D1 (de) 2001-10-04
EP0684552A4 (en) 1996-12-04
CN1084496C (zh) 2002-05-08
HK1018167A1 (en) 1999-12-10
CN1117764A (zh) 1996-02-28

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